JPH0374044U - - Google Patents

Info

Publication number
JPH0374044U
JPH0374044U JP13580189U JP13580189U JPH0374044U JP H0374044 U JPH0374044 U JP H0374044U JP 13580189 U JP13580189 U JP 13580189U JP 13580189 U JP13580189 U JP 13580189U JP H0374044 U JPH0374044 U JP H0374044U
Authority
JP
Japan
Prior art keywords
data
input
address
converting
storage section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13580189U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13580189U priority Critical patent/JPH0374044U/ja
Publication of JPH0374044U publication Critical patent/JPH0374044U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例の構成を示すブロツ
ク図、第２図は本実施例における真理値表を示す
図、第３図は従来例を示すブロツク図である。 １……データドライブ回路、２……ＲＯＭ制御
回路、３，２７……計数出力データ、４〜７……
インバータ、８〜２３……オアゲート、２４，２
５，２６……アンドゲート。 FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a truth table in this embodiment, and FIG. 3 is a block diagram showing a conventional example. 1...Data drive circuit, 2...ROM control circuit, 3, 27...Count output data, 4-7...
Inverter, 8-23...OR gate, 24,2
5, 26...and gate.

Claims (1)

【実用新案登録請求の範囲】 １ 複数の入力データからなる入力群をアドレス
入力に変換する手段と、前記アドレス入力に対し
、それぞれのアドレス毎にそのアドレス入力の各
ビツトの論理レベルの係数結果を予め決めたデー
タに定めて記憶した記憶部と、その記憶部の定め
たデータを出力するデータ出力手段を設けたメモ
リを有し、 前記複数の入力データに対して、そのデータの
論理レベル数を認識してそれに対応した計数デー
タを出力することを特徴とする論理状態計数回路
。 ２ 前記メモリをＲＯＭで構成したことを特徴と
する請求項１記載の論理状態計数回路。[Claims for Utility Model Registration] 1. Means for converting an input group consisting of a plurality of input data into an address input, and a means for converting a logic level coefficient result of each bit of the address input for each address. A memory including a storage section storing predetermined data and a data output means for outputting the predetermined data of the storage section; A logic state counting circuit characterized in that it recognizes and outputs counting data corresponding to the recognition. 2. The logic state counting circuit according to claim 1, wherein the memory is constituted by a ROM.
JP13580189U 1989-11-21 1989-11-21 Pending JPH0374044U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13580189U JPH0374044U (en) 1989-11-21 1989-11-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13580189U JPH0374044U (en) 1989-11-21 1989-11-21

Publications (1)

Publication Number Publication Date
JPH0374044U true JPH0374044U (en) 1991-07-25

Family

ID=31683044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13580189U Pending JPH0374044U (en) 1989-11-21 1989-11-21

Country Status (1)

Country Link
JP (1) JPH0374044U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52150946A (en) * 1976-06-11 1977-12-15 Hitachi Ltd Sequential logical circuit
JPS63291108A (en) * 1987-05-23 1988-11-29 Nec Corp Processor
JPH02210579A (en) * 1989-02-10 1990-08-21 Kokusai Electric Co Ltd How to match digital information

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52150946A (en) * 1976-06-11 1977-12-15 Hitachi Ltd Sequential logical circuit
JPS63291108A (en) * 1987-05-23 1988-11-29 Nec Corp Processor
JPH02210579A (en) * 1989-02-10 1990-08-21 Kokusai Electric Co Ltd How to match digital information

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