JPH04100210A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To form a low-resistance polysilicon thin film by performing high- temperature doping at a low temperature. CONSTITUTION:B2H6 gas or PH3 gas is used as a doping gas for forming a p-type Si thin film or n-type Si thin film. The substrate temperature can be set at 150-250 deg.C, but about 180 deg.C is especially preferable. The internal pressure can be set at 0.8Torr. The RF frequency is set at 13.56MHz and the power density is set at 30-100mW/cm, preferably 63mW/cm<2>. The mixing ratio of SiH4 with the doping gas is within a range of 10%>= (doping gas)/(SiH4)>=0.1% in the gas flow ratio and it is especially desirable to set the mixing ratio at about 2-5% for B2H6 (p-type) and about 0.5% for PH3 (n-type). When the gas flow ratio is <0.1%, the dropping effect of the resistivity after activating anneal becomes small and the resistivity does not differ much from the resistivity of doped polysilicon formed by thermal diffusion, since the gas flow ratio is smaller than the solid solution limits of B and P against Si.

Description

[Detailed description of the invention] [Fields of use of M soil collection] The present invention relates to a semiconductor device.

[Prior art] Polycrystalline silicon (poly-3i) thin film transistor (
TPT) has been attracting attention in recent years because it can be applied to large-area electronic devices, liquid crystal displays, and image sensors. In applying TPT to large-area device ice, it is important to reduce the wiring resistance of TPT, and especially in the case of MOS type TPT, it is important to reduce the resistance of the gate electrode. Poly-8i TFTs can also be applied to integrated circuits fabricated on Mata Si wafers. In this case as well, with the miniaturization of integrated circuits, lowering the wiring resistance has become an important issue.

Conventionally, the TPT gate electrode is a Cr electrode, doped)-p
Oly-si electrodes and the like have been used. In addition to the above-mentioned doped poly-8i, metal silicide and the like have been used for gate electrodes for MOS transistors in Si integrated circuits.

[Problems to be Solved by the Invention] Doped poly-3i has conventionally been generally formed by doping impurities by thermal diffusion. However, with this method, it is not possible to dope the impurity in the semiconductor thin film at a high concentration close to the solid solution limit. Therefore, the resistance p is low.

Since 1y-3i is formed, high concentration doping cannot be performed and the resistivity cannot be lowered. Further, metal silicide often has a two-layer structure of metal/silicide in order to lower the resistance, but this two-layer structure electrode has a problem in that it is brittle and easily breaks.

To solve this problem, Journal of A
p-plied physics vol, 66, n
o, 10. There is a method of creating a low-resistance Sil film by an in-situ doping method using low-pressure chemical vapor deposition (LPGVD), as seen in, e.g., p., 4812 (1989). Also Japanese Journal of A
pplied Physics, part 2, vo
There is also a method of activating the dopant using a laser annealing method, as shown in 1987, Vol. 1, 26° no. However, even in the LPCVD method, the temperature of the dopant in the semiconductor thin film depends on the substrate temperature during film formation, making it difficult to do high concentration doping at low temperatures. Furthermore, in the laser annealing method, it is difficult to scan a thin film formed over a large area in a short period of time, which poses a problem in mass production.

The present invention solves the above-mentioned problems, and its purpose is to provide a method for manufacturing a low-resistance poly-3i thin film formed by high-concentration doping at low temperatures.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes: (1) a method for thermally annealing an amorphous semiconductor into which impurities have been introduced to transform it into a crystalline semiconductor; A method for manufacturing a semiconductor device, comprising at least a first annealing step of annealing at a predetermined temperature T1 for a predetermined time.

(2) The first annealing step and the predetermined temperature T1
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a second annealing step of annealing for a predetermined time at a constant temperature T2 having a relationship of T1≦T2.

(3) The first or second annealing step is performed at a temperature T1≦
Thermal annealing is started at a temperature T3 having the relationship of T3,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the annealing step is one in which the thermal annealing is terminated at a temperature T4 such that ≦T4.

(4) The amorphous semiconductor film is formed using a mixed gas in which a mixture of impurity doping gas and the amorphous semiconductor film forming gas is set in a range of 0.1% or more and 10% or less. do.

(5) The amorphous semiconductor is produced by plasma chemical vapor deposition or reduced pressure chemical vapor deposition.

[Example 1] Hereinafter, an example will be explained through the method of manufacturing a semiconductor device of the present invention based on FIG. 1. In this example, Si will be used as an example of a semiconductor, but Ge, 5iGe, etc. The same applies. Furthermore, although a thin film transistor (T, F T '') is taken as an example of the semiconductor device of the present invention, the application example is not limited to TPT, but can also be applied to integrated circuit elements (IC, LSI) etc. formed on a crystalline Si wafer. Of course, the same applies.

First, a plasma chemical vapor deposition method (P
CVD) or low pressure chemical vapor deposition (LPCVD) to form an amorphous or polycrystalline Si thin film of about 1,000 to 1
500A film is formed. The substrate is not limited to quartz, but also low melting point glass substrates (MgO, Al2O3, CaF2, BP, etc.)
Crystalline P-edge substrate-c is also good. After etching this Si thin film into the pattern of the channel region 101 of the TFT, S
Approximately 300% of Si○2102 for the gate insulating film is deposited on the i thin film.
~500 people will be formed. A thin film on this Si○2 thin film - a
-3i thin film 103 is deposited at approximately 3000 to 7000A.

In the a-3i doping method, compared to the conventional doping method of thermally diffusing PCI O3 gas into poly-3i, the PCVD method requires changing the flow rate ratio of the doping gas and SiH4 gas. This allows the doping concentration to be set relatively freely. Therefore, there is an advantage that high-temperature doping with an impurity atomic temperature of several percent or more can be easily performed.

On the other hand, Ph 5ics and Technolo
of Sem1con-ductor Device
S, A, S, Grove, (1967) p, 11
3. Fig.

As shown in 4.14, the resistivity of n-type Si tends to be saturated when the impurity concentration relative to silicon is I x 10-''cm-3 or more, whereas the resistivity of p-type Si continues to decrease. When the impurity concentration is about 2.5 x 102 °cm-3 or more, the resistivity of n-type and p-type is reversed. Conventional thermal diffusion methods cannot easily perform doping in such a high temperature region, so for example, lXl0-' in p-type Si
A low resistivity of Ω·Cm−3 could not be achieved. However, according to the present invention using the P CVD method, the above-mentioned low resistivity can be easily achieved.

In this embodiment, the a-3i thin film 103 will be formed by using the PCVD method as an example. A mixed gas of SiH4, N2, and doping gas is used as the film-forming gas, and when forming a p-type Si thin film, B2H6 gas is used as the doping gas.
When forming a type Si thin film, PH and gas were used. The substrate temperature is preferably 150 to 250°C, particularly around 180°C. The internal pressure is 0°8 Torr. rf frequency 13.
At 56 MHz, the power density is 30-100 mW
/c~2.

In particular, 63 mW/cm2 is desirable, Si
The mixture of H4 and doping gas has a gas flow rate ratio of 10
%≧[doping concentration co/[SiH4]≧0.1%, in the case of B2H6 (p type), it is about 2 to 5%, and in the case of P H3 (n type), it is 0. About 5% is particularly desirable. When the gas flow rate ratio is less than 0.1%, it is smaller than the solid solubility limit of B and P in Si, so the effect of reducing resistivity after activation annealing, which will be described later, is small, and the conventional thermal diffusion method is not used. This is because there is no difference in resistivity from the doped poly-3i. In addition, if it exceeds 10%, impurity segregation may easily occur during the activation annealing process.
This is because, in particular, n-type a-3i is undesirable because it tends to cause film peeling from the substrate. p type a-3i,
In the case of B doping, the effect is great when the film is formed at a gas temperature ratio above the solid solubility limit.
The method is not limited to method D, and may also be an LPCVD method in which a mixed gas of 5i2Ha and B2H6 is thermally decomposed at a substrate temperature of about 450°C.
The a-5i is annealed to remove N2 contained in the a-5i. This is to prevent N2 from being rapidly desorbed and peeling of the film if activation annealing is performed while N2 is contained in a-3i. However, as will be described later, this 450° C. annealing can be omitted by appropriately controlling the rate of temperature increase up to activation annealing, which will be described later.

After this, the process moves to an activation annealing step. The annealing conditions are
Although it varies greatly depending on the dopant concentration of the doped A-3i thin film and whether it is n-type or p-type, it is generally 550 to 1000.
Annealing for several hours at a temperature of °C. However, when a low melting point glass substrate is used, the annealing temperature is limited to a process of 600°C or less. Table 1 shows an example of typical annealing conditions.

Table 1 The n-type annealing in Table 1 means annealing at 800° C. for 1 hour. N-type impurity temperature concentration 0. 5
% does not cause segregation of impurities even if the temperature is directly raised to 800° C., and a resistivity of about 6.0×10 −4 Ω·cm can be obtained.

The p-type annealing in Table 1 is step annealing,
The annealing temperature and annealing time in the table mean that after annealing at 600°C for 88 hours, annealing at 700°C for 16 hours, and then annealing at 800°C for 16 hours on the subsequent page. The reason for performing such step annealing is that if the heating rate is increased rapidly, the hydrogen remaining in the thin film will be released explosively, causing film peeling, so the hydrogen in the film is released slowly to prevent film peeling. This is to prevent the segregation of impurities. In particular, when doping with impurities at a high concentration, if the heating rate is fast or the initial annealing temperature is high, the dopants will segregate at grain boundaries, resulting in higher resistivity than low-temperature doped poly-3i. The purpose is to prevent this from happening. At the time of impurity activation, it is thought that impurity atoms enter the lattice positions from which hydrogen has escaped in the film, so the hydrogen release process is important.

The activation annealing method is not limited to the above-mentioned methods, but any method that has a heating rate and temperature that does not cause dopant segregation or abnormal diffusion to grain boundaries, etc., and a temperature cooling method that does not easily form a surface oxide film can be used. Any method is fine. For example, each annealing step does not necessarily have to be at a constant temperature6. If the temperature is T, the time is t, the initial annealing temperature is T3, the annealing end temperature is T4, and the annealing time is 10, then
An annealing process according to the temperature raising method expressed by the formula (%) may also be employed. In addition, if the annealing temperature is continuously raised during annealing, multiple annealing steps are not necessarily necessary, and the 450° C. pre-annealing and activation annealing described above may be performed in one annealing step. It is possible.

It is more desirable that the annealing time is sufficient to saturate the activation rate of the dopant. In addition, in order to obtain a low resistivity of about 1×IQ-4Ω・cm with p-type poly-3i, initial annealing should be performed at 550-600Ω.
Anneal at a relatively low temperature of about 0°C for more than 8 hours and then po
It is desirable that the average particle size of ly-3i be as large as 1 μm or more.

This is because when the crystal grain size is small, the length of the crystal grain boundaries included per unit volume becomes long, and when impurities segregate at the grain boundaries, this causes a large decrease in resistivity.

Figures 2 to 6 show examples of specific temperature raising methods in activation annealing. Figure 2 shows the n-type annealing method in Table 1, and Figure 3.4 shows the p-type annealing method in Table 1. These correspond to the respective annealing methods. FIG. 5 shows the step annealing shown in FIG. 3, with 600° C. annealing omitted. Although the crystal grain size obtained is smaller compared to the annealing method shown in Figure 3.4, it has the effect of shortening the time required for activation. FIG. 6 shows an annealing method applicable to n-type, which can shorten the annealing time the most. 2-6, for n-type, any method shown in FIGS. 2-6 may be used, and for p-type, method 3.4.
．． Any of the annealing methods shown in FIG. 5 may be used, however, FIGS. 2 to 6 merely show examples of annealing methods, and the methods are of course not limited to the methods shown here.

Furthermore, activation annealing is not limited to N2 annealing,
A rapid thermal annealing (RTA) method such as halogen lamp annealing may also be used. When the RTA method is used, the annealing time can be shortened to about 1 to 10 seconds.

Poly-
There are microscopically amorphous regions 104 at the grain boundaries of the 3i thin film.
remains. This amorphous region 104 at the grain boundary cannot be completely converted to crystalline even if the activation annealing time is increased, so in the case of an n-type sample, N2 annealing is performed at a stage after the activation annealing. 3 at temperatures above 900℃
0m1n.

It is desirable to do the above. This is because the resistivity can be further lowered by transforming an amorphous phase into a crystalline phase and further reducing the volume of the amorphous phase while keeping the crystal grain size large. This short-time annealing may be replaced by the step of forming a gate oxide film during TFT fabrication. Further, this short-time annealing method is not limited to N2 annealing, but may also be an RTA method using a halogen lamp or the like. When the dopant is boron, the N2 annealing temperature is less than 1000°C. This is because if N2 annealing is performed at a temperature of 1000° C. or higher, B atoms in the semiconductor will segregate at grain boundaries, and the resistivity will increase instead.

As a result, the resistivity of the polycrystalline Si gate electrode is n-type 0.
6.0 to 7.5X10-'Ω・cm% p for 5%
A value of 1.0 to 1.2×lOΩ・cm was obtained for the 5% type, and n-type poly-3 by the conventional thermal diffusion method was obtained.
Compared to the resistivity of i, 2.5X10-3Ω・cm, l/
A low resistivity of 4 to 1/20 can be obtained. Although it is difficult to create a semiconductor having a resistivity of 1.0×10 −3 Ω·cm or less using the conventional thermal diffusion method, the present invention makes it possible to easily create a semiconductor having the above-mentioned resistivity. In addition, the PCVD method allows high-temperature doping at a relatively low substrate temperature of 150 to 300°C, so if the resistivity is the same as that of the conventional thermal diffusion method, it can be achieved with activation annealing at 600°C for 8 hours. can. Therefore, a low-cost, low-melting point glass substrate can also be used.

Furthermore, since a furnace annealing process is used for activation annealing, it is superior in mass productivity compared to the laser annealing method. In addition, since poly-3i has better step coverage and is less likely to cause disconnection than a metal/silicide two-layer structure electrode, it will lead to improved reliability if applied to ICs, LSIs, etc.

Next, ion implantation is performed with P4' ions in the case of an n-channel TPT and B1 ions in the case of a p-channel TPT using the gate electrode as a mask.
7 and a drain region 106 are formed. After this, the sauce
This activation annealing, in which thermal annealing is performed at 900° C. for the purpose of activating the drain, simultaneously achieves complete activation of the dopant in the gate electrode 105 and an increase in the crystallization rate. The a-3i film for the gate electrode is formed using μwave Blaz 7CVD (ECRCVD) (11U) (7)
is also suitable. The a-3i film formed by ECRPCVD is
Since the hydrogen content in the film can be reduced, there are advantages in that the briant annealing for H2 elimination can be omitted and the activation annealing time can be shortened.

Next, an interlayer insulating film of S is deposited on top of this by low pressure CVD.
i O2 film 108 is formed to a thickness of about 800 OA.

The glabella insulating film may be a Si nitride film, etc. At this stage, if hydrogen ions are introduced into the active layer by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film, gate insulation This has the effect of terminating dangling bonds existing at the film/Si interface, grain boundaries, etc., and reducing defect level density. Such a hydrogenation step may be performed before laminating the glabellar insulating film.

Finally, contact holes for the source and drain are opened, and a metal film (such as AI) for the wiring material is formed using a sputtering method of approximately 8000A, and a source electrode 110 and a drain electrode 109 are formed.
Patterning completes the TPT.

Since the hydrogenated channel layer poly-8i exhibits properties slightly more n-type, an n-channel TPT using an n-type poly-3i gate electrode exhibits vth of about -IV,
There was a problem that the OFF current was large. p-type pol
When using y-8i for the gate electrode, n-type poly
-3i, the threshold voltage vth of the TPT shifts to the positive side by about 1v in the n-channel TPT.

Therefore, vth of n-channel TPT is near ov,
The increase in OFF current can be suppressed. Also, p-channel TPT
In this case, compared to the n-channel, the shift of vth is less likely to occur, and the vth, which originally shifted in the positive direction, only comes around Ov, so the OFF current does not increase.In this way, the p-type poly-3i gate electrode is If used, the advantage is that the channel doping step required to suppress the vth shift in conventional hydrogenated TPT is not required.

Furthermore, the present invention can also be applied to highly integrated SRAMs of 4 megabits or more. “IEICE Technical Research Report J Vol. 90. No. 48, p. 7, p.

As shown in 75 etc., SRAM memory cells have conventionally used a cell structure with a high resistance load.
By replacing it with PT, stable data retention and low power consumption characteristics can be realized.
When applied to AM TPT, low resistance poly-3i gate electrodes can be freely created for both n-type and p-type, so S
This is a great advantage for increasing the integration of RAM.

[Effects of the Invention] According to the semiconductor device of the present invention, reduction in gate wiring resistance, which has been difficult with doped poly-3i using the conventional thermal diffusion method, can be easily achieved through extremely simple steps. Furthermore, since the PCVD method has the advantage of being able to form a uniform thin film over a large area, it can also be applied to large liquid crystal panels. Furthermore, the gate wiring resistance of TPT can be reduced, making it easier to apply liquid crystal panels to high-quality TVs. Furthermore, it is possible to make the contact type image sensor longer in which the scanning circuit and the charge conversion element are integrated on the same substrate, which has a great effect on increasing the size of the image sensor. Similarly, applications to TPT-driven liquid crystal shutter arrays, TPT-driven thermal heads, etc. are also possible. Moreover, it is possible to apply not only to TPT but also to highly integrated SRAM, three-dimensional SOI elements, etc.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the manufacturing process of a semiconductor device of the present invention. 2 to 6 are diagrams showing an example of an activation annealing method in the method of manufacturing a semiconductor device of the present invention. 100...Quartz substrate 101...Channel region 102...
......Gate insulating film 103...N10 amorphous [5i104...Amorphous gate electrode 105...Polycrystalline Gate electrode 106...
......Drain region 107...
Source region 108...Interlayer insulating film 109...Drain electrode 110...
... Source electrode Figure 3 Time (min,) Figure 5

Claims (5)

[Claims] (1) In a method of thermally annealing an amorphous semiconductor into which impurities have been introduced to transform it into a crystalline semiconductor, a first annealing step is performed in which the amorphous semiconductor is annealed at a predetermined temperature T1 for a predetermined time. A method of manufacturing a semiconductor device, the method comprising: (2) The first annealing step and the predetermined temperature T1
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a second annealing step of annealing for a predetermined time at a constant temperature T2 having a relationship of T1≦T2. (3) The first or second annealing step is performed at a temperature T1≦
Thermal annealing is started at a temperature T3 having the relationship of T3,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the annealing step is one in which the thermal annealing is terminated at a temperature T4 such that ≦T4. (4) The amorphous semiconductor film is formed using a mixed gas in which a mixture of impurity doping gas and the amorphous semiconductor film forming gas is set in a range of 0.1% or more and 10% or less. 2. The method of manufacturing a semiconductor device according to claim 1. (5) The method for manufacturing a semiconductor device according to claim 1, wherein the amorphous semiconductor is produced by plasma chemical vapor deposition or low pressure chemical vapor deposition.