JPH0411046B2 - - Google Patents

Description

[Detailed description of the invention] (Technical field) The present invention relates to a clock signal generation circuit.

(Prior Art) Examples of a conventional clock signal generation circuit of this type and its successor circuit, and their timing charts are shown in FIGS. 1 and 2, respectively.

The clock signal generation circuit and its subsequent circuits in FIG.
It consists of

When the rising edge of the signal 1a shown in FIG. 2 is input to the clock terminal A of the circuit shown in FIG.
and falls via inverters 13 and 11,
It becomes a low level (hereinafter referred to as L level) and changes like the signal 1c in FIG. 2.

Next, the output signal 1d of the inverter 14 rises from the signal 1c through the NOR gate 15 and the inverters 16 and 14, becomes high level (hereinafter referred to as H level), and changes like the signal 1d in FIG. 2. Signals 1c and 1d are used as internal clock signals, and as indicated by "L" in FIG. 2, both signals are at L level for a certain period of time.

However, the line that transmits the output signals 1c and 1d of the clock signal generation circuit section 200 has resistances R ₁ and R ₂ corresponding to wiring resistance, wiring capacitance, and gate capacitance as shown in the clock line section 201 as loads. There are capacitances C ₁ and C ₂ corresponding to At the same time, it may become H level.

Now, if the clock signals 1f and 1g, which have become H level for a certain period of time, are input to the shift register section 202, the signal 1h applied to the input terminal B of the shift register section 202 will be transferred to the transfer gate 110 at the rising edge of the clock signal 1g. This becomes the input signal of the inverter 18, and the output signal 1i changes as shown in 1i in FIG. Here, the output signal 1j of the inverter 19 should change at the rising edge of the clock signal 1f, but since the clock signals 1f and 1g are at H level at the same time, the output signal 1j
i, which causes a malfunction (the broken line portion of signal 1j in FIG. 2 shows the waveform during normal operation).

If the operating speed of the inverter 18 is slow enough, the output signal 1j will be the clock signal 1f.
The circuit operates normally as shown by the broken line of signal 1i in Figure 2 without changing until the rising edge of There is a drawback that even if the time of the "H" portion in FIG. 2, which is the overlapping portion of the clock signals, is short, a malfunction may occur.

In addition, in order to prevent malfunction, "L" in Figure 2
If there is a sufficient interval between the clock signals 1c and 1d shown as , the pulse width of the clock signals 1d and 1c becomes small, making them unsuitable for high-speed operation.

(Object of the invention) The object of the invention is to
It is an object of the present invention to provide a clock signal generating circuit which allows subsequent circuits to operate stably without malfunction under operating conditions such as a wide range of power supply voltages by changing the time ratio to the level in accordance with the power supply voltage.

(Structure of the Invention) The circuit of the present invention includes first and second logic gates having first, second and third input terminals, respectively;
The basic clock to be supplied is input to the input terminal of , the first delayed output of the second logic gate is input to the second input terminal, and the first delayed output of the second logic gate is input to the input terminal of the second logic gate. A clock that is an inverted version of the supplied basic clock is input to the terminal, and the first delayed output of the first logic gate is input to the second input terminal, and when the supply voltage is above a certain value, third and fourth logic gates that input second delay outputs delayed from the first delay output to the third input terminals of the first and second logic gates, respectively; It is composed of

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing one embodiment of the present invention.

The clock signal generation circuit section 300 in FIG. 3 includes a NOR gate 21 and an inverter 22 which receive the signal 2a at the clock terminal C as an input signal, and inverters 23, 24, 26 and 27 which delay the signal.
, inverters 25 and 28 that delay the rise of the signal, NOR gates 29 and 210, capacitors _C3 and _C4 , and a control terminal D that supplies a signal to control the output of the NOR gates 29 and 210. .

First, a case where the power supply voltage is high and there is a risk of malfunction even if the clock signals overlap for a short time will be described.

Input an L level signal to control terminal D,
The output prohibition of NOR gates 29 and 210 is canceled, and the rise of NOR gates 211 and 21 is delayed by signals 2n and 2m having a certain period of delay created by capacitor C ₄ of inverter 25 and inverter 28 and capacitor C ₃ . This makes it possible to narrow the pulse width of the clock signal and eliminate the simultaneous H level overlap of the clock signals 2f and 2g, thereby preventing malfunctions in subsequent circuits.

In the above case, the pulse width will be narrower, but under conditions where the power supply voltage is high and a small amount of simultaneous high-level clocks will cause a malfunction, the operating speed of the circuit will be faster and the pulse width of the clock signal will be narrower. It works perfectly fine though.

On the other hand, when the power supply voltage is low, the operating speed of the circuit is slow and even if some clock signals are simultaneously at H level, the circuit will not malfunction. Therefore, high-speed operation can be achieved by inputting an H level to the control terminal D, reducing the interval indicated by "L" in FIG. 2, and increasing the pulse width of the clock signal accordingly.

In this embodiment, a control terminal is set to receive a control signal supplied from the outside, and the interval between clock signals is changed. However, if the clock signal generation circuit is built in a microcomputer or the like, It is obvious that the control terminal can be omitted and changes can be made by executing instructions.

(Effects of the Invention) The present invention has the advantage that by changing the pulse width of the clock signal depending on power supply voltage conditions, etc., it is possible to obtain a clock signal that operates stably without malfunction even under a wide range of operating conditions.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional clock signal generation circuit and its successor circuit, Fig. 2 is a time chart of the circuit shown in Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4. is the timing chart in FIG. 11, 13, 14, 16, 17, 18, 19,
22-28... Inverter, 12, 15, 21,
29, 210, 211...NOR gate, R ₁ ~ _{R 4}
...Resistance, C ₁ to C ₆ ...Capacity, 110,111...
... Transfer gate, 200, 300... Clock signal generation circuit section, 201, 301... Clock line section, 202... Shift register section.

Claims (1)

[Claims] 1 first and second logic gates having first, second and third input terminals, respectively;
In the logic gate, the supplied basic clock is inputted to the first input terminal, the first delayed output of the second logic gate is inputted to the second input terminal, and the second logic gate is inputted to the second input terminal. In the gate, an inverted clock of the supplied basic clock is input to the first input terminal, and a first delayed output of the first logic gate is input to the second input terminal. a third and second delay output delayed from the first delay output to the third input terminal of each of the first and second logic gates when the power supply voltage is above a certain value; A clock signal generation circuit comprising a fourth logic gate.