JPS59158656A - Serial data transmitter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is applicable to the field of control communication, for example, where a plurality of data are generated at any time, the state within a certain period of time is unchanged, and the period required by the next stage device is determined. Moreover, the present invention relates to a serial data transmitting device that transmits data sequentially in series.

Conventional configurations and their problems Recently, as society has become more sophisticated and complex, the need for advanced information and communication systems that can provide a large amount of information has become increasingly important. The system usually has a large number of information storage devices and a large number of terminal devices, and the control and communication of these devices is
It takes the form of a PU (central processing unit), and may also be networked. In such advanced information and communication systems, the communication control data is also complex and requires high transmission speed and reliable communication methods.Especially in the case of long-distance communication, there is a large possibility of signal delay, and data It is necessary to provide a means for imparting some regularity to the transmission method.

However, conventional serial data transmitting devices are either synchronous type devices having a shift register or counter, or asynchronous type devices such as an arbiter in a multiprocessor system. Therefore, the former synchronous method requires all sampling clocks and shift pulses, and because reception and transmission are synchronized, it is not possible to use a flock or shift pulse with a cycle faster than the serial transmission cycle, and all data are processed regardless of the presence or absence of data. It was necessary to check the data line, making it difficult to speed up the data reception cycle. Furthermore, a periodic signal was required to synchronize transmission and reception.

Furthermore, the latter arbiter also needs to check the request signals of all cells, which requires time and shift pulses, making it difficult to speed up the data transmission cycle.

Purpose of the Invention The present invention has been made in view of the above-mentioned problems, and its purpose is to enable high-speed reception and transmission without requiring a sampling clock or shift pulse for data reception. Moreover, it is an object of the present invention to provide a serial transmitter that can transmit data in synchronization with an arbitrary transmission cycle without requiring a synchronization signal for synchronizing reception and transmission.

Structure of the Invention The present invention provides a first latch means for received data, a first priority line selection means, a second launch means for a second priority line λ, a second priority line selection means, This relates to a device equipped with a clear data memory, a data clear signal generating means, and an interrupt controller, characterized by having an interrupt control device that transmits data in synchronization with an arbitrary transmission cycle or with a self-cycle. It is something to do.

That is, the first latch means stores received data at the same time as it is generated, and enables reception of a plurality of data whose states are not required within a certain period of time and high-speed, simultaneous reception. The first line selection means determines the first priority of the data stored by the first launch means and transfers only the data with the highest priority. The second launch means stores all the data selected by the first line selection means for a certain period of time, and stores the data even if the output signal P I of the first line selection means changes before data transmission is completed. It makes it possible to transfer everything without losing it. The second line selection means determines the secondary priority of the data stored by the second latch means, and transmits only the data with the highest priority. However, the priority order of the first order and that of the second order are completely reversed, and the selected data is held in the hole where the transmission is completed. The clear data storage means stores the data transmitted to the CPU and transmits it to the data clear signal generation means. When the CPU completes reception, the data clear signal generation means
A signal is generated to clear all the data received by the first
The signal is sent to the second latch means.

The interrupt control means receives an AC signal from the CPU, generates an interrupt signal in synchronization with the signal, controls the clear data storage means and the data clear signal generation means, and also controls the self-control when an ACK signal is not received. Interrupt control is performed according to the period.

With the above configuration, it is possible to perform synchronous transmission in which all data is transmitted in synchronization with any transmission cycle required by the next-stage device, without depending on the data reception cycle. Since pulses or synchronization signals are no longer required, the circuit becomes simpler and the device becomes smaller, and furthermore, it becomes easy to adapt to any next-stage receiving device.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

Note that as an embodiment of the present invention, a VTR control device (hereinafter referred to as VT
A case in which the present invention is applied to RC (abbreviated as RC) will be explained.

FIG. 1 shows the entire configuration of the VTR control system, and FIG. 2 shows the VTR control system communication diagram showing the types of communication data and signals necessary for controlling the entire system and their flows.

In FIGS. 1 and 2, the VTRG 20 is the CPU 10
7) Receives the command data of
All 74a are selected and represent the movement g' of the vTR of the 24 VTR group 3o.jLAMP signals 510 to 740, and the Gue tone 51 represents all the running positions of the VTR tapes.
C to 74 C are received, and the dynamic change of the VTR and the entire status of the cue signal signal are transmitted to the CPU 10, and the entire dynamic state of the VTR is displayed. Here, as shown in FIG. 2, the command data is a 5TB (strobe) signal 42.
(!: Consists of VTR address command 43, status data 1RT (interrupt) signal 44, and VTR address medium status 45.Furthermore, FIG. 3 shows a bit map of the communication data between the CPU and 4TRC. .Here, upstream data B-lower 11)-r-1'A#
VTR7doL/S43a.

Only 45a is a binary number, and the others correspond to bits. Mafl A G K (Acknowledge)
The signal 46 is the RIC generation occurrence RDY (Ready) signal 4 when the CPU 1o has completely completed receiving the status data.
-+ Indicates that HHvrRc20 is ready for reception. still,
In the above system, four types of commands and five types of status are communicated.

In the above configuration, command data transmitted from the CPU 10 is first received by the receiver 100. The receiver 100 receives the VTR address 43 in the command data.
fL is decoded to generate a switch signal 141 for each VTR and each command 43b. This switch signal 14
1 is transmitted to the VTR switch isolator 200.

VTR switch isolator 200 connects VTRC20 and V
The TR group 30i is electrically isolated and all signal levels are converted, and the VTR switch signal 231 is connected to each VTR of the entire VTR group 3°.
Selected as TR. In addition, yTRL showing the dynamics of each VTR
AMP signal 311 is connected to VTRLAMP isolator 300
is input to. This Izley'1300IdVTR group 30 and VTRC20'i are electrically isolated and the signal level is completely converted, and 5TOP of the status 456
It generates a signal and a PLAY signal, and transmits a status signal 341 to the status display 400 and Transmino Taro 00. Incidentally, this status signal 341 is a signal that changes in synchronization with changes in the dynamic state of the VTR, and while the VTR maintains one dynamic state, the status signal 341 is also held and does not change. On the other hand, Cu represents the running position of the VTR tape.
E-tone 511 is input to cue signal generator 500. This cue signal generator 500 is used for each "/" of the VTR group 30.
The audio output terminal of the TR and the VTRC 20 are electrically insulated, the audio signal level is amplified, and all the audio signals are detected and their durations are checked. If the signal exceeds the set time, the TTL signal is sent as a cue signal. 541, and further transmits a cue signal 541'i) to Ransminotaro 00.

Finally, the transmitter 00 receives the plurality of status signals 341 and the plurality of cue signals 641 at any time and in parallel. Due to this reception, Transmino Taro 00
encodes all the received signals, that is, generates VTR addresses 45ai for distinguishing all the VTRs in the VTR group 30 that are the generation sources of the received signals, and also generates the iRT signal 44 and synchronizes with the AC signal 46. This is set when the ACK signal 46 is not received, and the status data is transmitted periodically.

This status data is sent to CPU1 in synchronization with CPU10.
Sent to 0.

Control communication of the VTR control system is performed as described above.

Hereinafter, the operation of each part of Transmitaro 00 will be explained based on FIG. 5, which shows the blocks of Transmink 600 and the flow of signals.

First, the plurality of child data signals 341 and cue signals 5411'i described above are input in parallel to each independent input vanofer 710. These status signals 341 and Cue
The signal 541 is a signal that occurs at any time and has the property that it is maintained and does not change for a certain period of time when the /TR maintains one dynamic state. Therefore, the case where a plurality of signals are received at the same time must also be considered.

Next, the status signal 341 and the cue signal 541U1,
Priority transfer circuit 8 via input Hanofu 710
It is input to the GK (clock) terminal of each cell of the primary latch element 810 in 00. Here, in this system, since the D (data) terminal of each cell of the latch element 810 is not used, the status signal 341 and the cue signal 541 are stored in each cell of the latch element 810 at the same time as they are generated. The output of the cell is input to a primary line selection element 820 having a BRIRITALIO function. Line selection element 820 simultaneously inputs i''
Outputs only the highest priority signal among the plurality of signals given in accordance with a predetermined priority order.

The output signal of the line selection element 820 is transmitted to the second launch element 8.
The signal is input to the GK terminal of each of the 30 cells and stored. Here again, the output signal of latch element 830 is input to encoder 840 having a priority function. In the Ling system, the encoder 840 is used as a secondary line selection element. Here, as described above, the line priority determined by the primary line selection element 820 is determined by the encoder 84.
The line priority order is completely opposite to the line priority order determined by 0.

Next, the encoder 840 encodes the encoded output signal, ie, the address signal 840a, and the G S (Groupe S
θ1ect) The output signal 840b is both output Banoff,
-760 (Sent to CPU 10 via H.

In this case, the address signal 840a is VTR address 4.
5a as the signal of the lower three digits, and the Gs output signal 840
b is sent to cptzo as -t with status 45b. On the other hand, the address signal 840a and the GS signal 840
b is transferred to clear data memory 740 as data to be stored.

Further, the GS signal 840b is input to the secondary encoder 730 via the address signal f720.

Here, the address switch 720 selects the VTR group 30 from the VTR group 30.
This is a manual switch for dividing the machines into groups of a units and setting the number of groups in advance. If
The c encoder 730 encodes the line signal set by the address switch 720, and the output signal encoded by the encoder γ30 is transmitted to the CPU 10 as a signal of the upper three digits of the VTR address 452L via the output Hanofuma γ60i.

Next, the GS signal of the encoder 730 is sent to the interrupt controller 900.
The one-shot pulse generated as a full trigger is input to the output buffer 7760 and transmitted to the CPU 10 as a h i RT signal, while the one-shot pulse is input to the clock terminal of the clear data memory 740 and output to the encoder 840. This serves as a clock signal for the clear data memory 240 to store the address signal 8402L and the Gs signal 840b. The signal stored in the clear data memory 740 is then input to the output line selection terminal of the data clear signal generator 750. Next, when the CPU 10 completes receiving the status data, A
The CK signal 46 is sent to the transmitter 00, and the AC signal 46 is sent to the interrupt controller 90 via the input buffer 710.
The force input to 0 is ru.

The one-shot pulse generated as the ACK signal 46i and IJ signal is the Ena signal of the data clear signal generator 750.
Input to the ble terminal 'h,, using this as a trigger, data clear signal generator 750d: data clear signal 75
1 and its data clear signal is sent to the latch element 810.
．． a30 and clear the data of each cell that stores the status signal corresponding to the status data sent to CP TJlo. As described above, the interrupt controller 900 transmits the status data to all cptzos in synchronization with the data signal 7, and clears the status signal in synchronization with the interrupted ACK signal 46. Here, the transmitter 00 generates the iRT signal 44 and the latch element 8
1 time to clear 10,830 memory data gold
If Transmino Taro 00 receives multiple status signals in this unit time, the interrupt controller 900 clears all the transmitted status signals, and at the same time, the encoder 840 sends the status with the next priority. A signal is output and transmitted to the status data CPU 10 through the same procedure as described above. In this way,
The status data is sequentially transmitted in synchronization with the ACK signal 46. This transmission synchronous serial data transmission system will be described in detail below with reference to the drawings.

FIG. 6 shows a signal flowchart of the interrupt control circuit. Status signal 83 stored in secondary latch element 830
1 are all input to the Brioli theme encoder 840,
Among them, only the signal with the highest secondary priority is output. Its output signal is a binary encoded signal 840
a, 0-a2.

G S (Groupe 5e
This GS signal 840b is a signal indicating the group to which the VTR generated in the status signal 831 belongs, and the status signal 831 is a signal of the same type 1, for example, all play (PLA
Since it is a status signal of Y), it is also the status 456 sent to the CPU 10. On the other hand, the binary signal 84
0? LO-A2 is a signal indicating the relative address of the VTRs in the same group, and the VTR to be sent to the CPU 10.
T R7)"1/s 45a is transmitted as the last three digits.

These four signals, GS signal 840b and binary signal 84
0 al to a2 are transmitted to the clear data memory 240, and are stored in the clear data memory 740 for a certain period from a certain point.
latched to. Furthermore, the GS signal 840b is the data clear signal generator 750ff: enable (TLnable).
) and is transmitted to the address switch 720.

This address switch 720 is used to set in advance the group Nα to which the VTR that has generated the status signal 831 belongs, and the GS signal 840b is sent to the encoder corresponding to the 7"1 line set by the address switch 720. It is input to the input terminal of 730.

The encoder 730 receives a GS signal 840b, a signal encoded in full binary numbers, and a GS signal 730 that indicates the presence or absence of the input signal.
The former binary signal that outputs b is sent to the CPU 10 as a signal of the upper three digits of the VTR address 45a.
10. On the other hand, the latter GS signal 730b is input to one trigger input terminal of the interrupt controller 900.

Here, the interrupt control circuit 900 is 'l''j constant Maru r-
It's an element with two built-in vibrator circuits, so 7
'1-2) IJ nof-large book terminal person and B, 2
Equipped with two output terminals Q and one CLR (clear) terminal, 1 person, 1B, 1Q.

1 mutual and 1cLR are for the first circuit, 2A, 2B.

2Q, 2Q and 2CLR are for the second circuit. and,
As shown in the figure, both people are grounded and 2CLR is pulled up to +5V. Furthermore, 1Q is input to 2B, and 2Q is input to 1B. Furthermore, in both the first and second circuits, when the input terminal B is at a high level, the signal input to the trigger input terminal A is inputted, respectively, when the signal input to the trigger input terminal A reaches its peak, and on the other hand, When the trigger input terminal A is at a low level, the signal input to the trigger input terminal B is retriggered at the rising edge of the signal, and the output terminals Q and A of the first and second circuits receive the entire one-shot pulse signal. Output. Here, the output Q signal is a high level pulse, and the output page signal is a low level pulse. Therefore, when the encoder 730 generates all the GS signals 730b, the first circuit is triggered and outputs a one-shot pulse signal from the iQ+1 terminal output. The output signal of 1Q is appropriately delayed by the delay circuit 910, and sent to the CPU 10 as the iRT signal 44 via the output banfu, and is also input to the GK terminal of the clear data memo I7740; 84
0 output signals 840b and 840a1-2L2 are latched into clear data memory 740. Next, the 1-enabled output signal of the interrupt controller 900 is input to 2B, and the 1-enabled output signal is input to 2B.
When the second output signal rises, that is, the time set by the first circuit constant has elapsed, the second circuit is triggered and the second interrupt controller 900 outputs a one-shot pulse signal of LOW level from 24. These two output signals are input to the Enable terminal G2A of the data clear signal generator 750. Therefore, at the same time that the output pulses of the two stations are generated, the data clear signal 751 is generated from the selected output terminal f'L of the data clear signal generator 50. Data A and B for line selection in Data Clear Low Gin Occurrence Booklet 60
.

C is the latch output of the clear data memory 740 and CP
This is the same data sent to U10. Therefore,
A data clear signal 751 is input to the CLR (clear) terminal of the corresponding cell of the first and second latch elements that have accumulated all the data transmitted to the GP Ulo, and erases the accumulated data. As described above, the status signal 831 is
It is sent to the PU and deleted after the set time has elapsed.

Here, a case where the CPU 10 receives the ACK signal 46 transmitted as a data reception completion signal within the set time will be described. When the 1Q output signal of the interrupt controller 900 is delayed by the delay circuit 910 and transmitted to the CPU 10 as the iRT signal 44 via the output panopher, the CPU 1
0 reads all of the status data (VTR address status) at the falling edge of the iRT signal, that is, at the time of generation, and issues an ACK signal 46 when the arithmetic processing is completed. This human CK signal is input to the 1CLR terminal of the interrupt controller 900.

At this input point, the 1Q and 1 enable output signals of the interrupt controller 900 are cleared and returned to the initial state. That is, 1Q11-I L
%ow level, 1 level becomes High level. Furthermore, the time when 1 possible changes to High level, that is, ACK
At the input of the signal 46, the second circuit is triggered and a pulse is output from the second circuit. The subsequent operations are as described above. In this way, it is possible to transmit and erase data regardless of whether or not the ACK signal 46 is input.

The next Vc1 status signal 831 is transmitted within a unit transmission time, that is, within the time period 1 from when the first circuit output of the interrupt controller 900 is generated to when the second circuit output disappears, a plurality of status signals 831 are continuously transmitted. A case where the signal is input to the primary encoder 840 will be explained.

As described above, at the same time that the two output signals of the first interrupt controller 900 are generated, the data clear signal 751 is generated.
When the data transmitted to the PU 10 is cleared, the encoder 840 outputs data with the next priority. The output signal is sent to the primary encoder 840 [C input rLG
When the s signal 730b is input to the IAK of the interrupt controller 900 (at this point, the signal output period is about 20 seconds), the first circuit is not triggered because 1B is at a low level. And at the end of the output signals of the two, one person is Lo.
Since it is at the w level, the first circuit is triggered at this point and the n, iRT signal 44 is transmitted to the CPU. If the output period of the ACK signal 46 is longer than the two output periods, the first circuit is not triggered at this point because 1-C and LR are at low level at the end of the two outputs. One person is in Lo at the end of the ACK signal.
Since 18 is at the high level in the w level, the first circuit is triggered at this point, and the output signal of is 1Q is transmitted to the CPU 10 as an iRT signal. In this way, A
Regardless of the length of the CK signal 46 generation period, the iRT signal 44 is not transmitted to the CPU 10 during the ACK signal generation period.

In the above manner, multiple consecutive input signals can also be
It is possible to transmit all data serially in synchronization with the transmission cycle required by o, that is, in a transmission synchronous manner.

Effects of the Invention As described above, according to the present invention, the first latch means enables the reception of a plurality of data which are generated at any time and whose state remains unchanged for a certain period of time, and furthermore, the first latch means has a priority function. By combining this with a selection means, there is no need for a summing clock or shift pulse for data acquisition, and the data line can be checked using only the data generation line, making it possible to receive multiple data at high speed and simultaneously.

Furthermore, by providing the second latch means and the second line selection means having the Briolite I function, there is no need for all shift pulses for transmission and there is no need to confirm data lines with no signal, so data can be transmitted. This made it possible to speed up the process. In addition, as in 1 or more, the latch means and the Briolite I
The combination with the line selection means having the function is arranged in two stages, and furthermore, the interrupt control means having the function of simultaneously erasing all the data stored in the first and second latch means in synchronization with the transmission cycle is provided. This eliminates the need for the same 1υ signal for the reception/transmission synchronization ratio, and transmits data in synchronization with any transmitting station jυ required by the next stage device without depending on the data reception cycle V. It is now possible to send all expressions. Since sampling clocks, shift pulses, or synchronization signals are no longer required, the circuit becomes simpler, the probability of malfunction due to noise is lowered, and the device is also made smaller.

Furthermore, by adopting a data clearing method in the interrupt control means that sequentially erases accumulated data at a set transmission cycle regardless of the presence or absence of a data reception completion signal from the next device, the data reception is completed. It is now possible to have an initializer function that does not necessarily require a signal and also erases all imaginary data using an IJ gar (noise generated when the device is powered on).

In addition, when using the data reception completion signal mentioned above, we have adopted a method that clears the accumulated data in synchronization with the reception completion signal, thereby increasing the speed of data transmission and dealing with variations in reception processing time of the next stage device. It became possible. In this way, by adopting the above-mentioned interrupt control means, it becomes easy to support all kinds of next-stage receiving devices, and since the initialization function circuit is no longer required, the circuit becomes simpler and the device becomes smaller. is a dog.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a VTR control system to which a serial data transmitter according to an embodiment of the present invention is applied;
The figure is a block diagram of the main parts of the VTR control system.
Figure A, BHCP U-VT RC communication data
・A diagram showing the map, Figure 4 is 10...CPU
, 20...VTR control device, 46...A
CK signal, '600/old...transmitter, 80
0...Priority transfer circuit, 81o°°゛'
°. Primary latch element, 820°°P line selection element. 830″′°゛°゛Second buffer memory, 840...
...Primary encoder latch element, 740...
・・Clear data memory, 750″゛°・°・Data clear signal generator. 900…Restriction controller, 730…Second encoder. Name of 111 people Patent attorney Medium Toshio O and 1 others
given name.

Claims (1)

[Claims] a first latch means for temporarily storing a plurality of received data generated from time to time; a first line selection means for assigning all first-order priorities to the plurality of received data stored by the first launch means; a second latch means for temporarily storing a plurality of received data preferentially selected by the first line selection means; and a second latch means for giving a second priority to the plurality of received data stored by the second latch means. clear data storage means for storing received data to be sent to the central processing control unit; and a data clear signal for generating a signal for clearing the received data sent by the clear data storage means to the central processing control unit. The generation means generates an interrupt signal in synchronization with the signal when it receives the clearance signal sent from the central processing control unit, controls the storage means and the data clear signal generation means, and further controls the reception data. Interrupt control means for transmitting data in synchronization with an arbitrary transmission cycle required by the medium heat control device without depending on the cycle, and transmitting the data in a self-cycle when the accelerator signal is not received. serial data transmitter.