JPH0466876U - - Google Patents
Info
- Publication number
- JPH0466876U JPH0466876U JP11042190U JP11042190U JPH0466876U JP H0466876 U JPH0466876 U JP H0466876U JP 11042190 U JP11042190 U JP 11042190U JP 11042190 U JP11042190 U JP 11042190U JP H0466876 U JPH0466876 U JP H0466876U
- Authority
- JP
- Japan
- Prior art keywords
- analog switch
- synchronization signal
- signal
- video signal
- pass filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 claims 1
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Synchronizing For Television (AREA)
Description
第１図及び第２図は本考案の一実施例を示し、
第１図はＰＬＬ回路を示す構成説明図、第２図は
第１図の各部の信号の関係を示すタイムチヤート
、第３図は従来のＰＬＬ回路を示す構成説明図、
第４図は第３図の各部の信号の関係を示すタイム
チヤートである。
１１……アナログスイツチ、１３，１６……ア
ンドゲート、１７……インバータ、１８……ノア
ゲート、１９……ローパスフイルタ、２０……電
圧制御発振器、２２……分周器。
1 and 2 show an embodiment of the present invention,
FIG. 1 is a configuration explanatory diagram showing a PLL circuit, FIG. 2 is a time chart showing the relationship of signals in each part of FIG. 1, and FIG. 3 is a configuration explanatory diagram showing a conventional PLL circuit.
FIG. 4 is a time chart showing the relationship of signals in each part of FIG. 3. 11... Analog switch, 13, 16... AND gate, 17... Inverter, 18... NOR gate, 19... Low pass filter, 20... Voltage controlled oscillator, 22... Frequency divider.
Claims (1)
、基準同期信号に従つて開閉される位相比較用ア
ナログスイツチと、 このアナログスイツチからの出力信号が積分さ
れるローパスフイルタと、 このローパスフイルタの出力電圧レベルに従つ
て発振周波数が制御され、基準クロツクを発生す
る電圧制御発振器と、 ビデオ信号の垂直帰線消去期間内は１Ｈ周期の
疑似水平同期信号を前記アナログスイツチの基準
同期信号とし、前記ビデオ信号の垂直帰線消去期
間外は前記ビデオ信号から得られた複合同期信号
を前記アナログスイツチの基準同期信号とする選
択回路と を具備することを特徴とするＰＬＬ回路。[Claims for Utility Model Registration] A phase comparison analog switch to which a comparison signal obtained from a reference clock is input and which is opened and closed in accordance with a reference synchronization signal; and a low-pass filter in which an output signal from this analog switch is integrated. , a voltage-controlled oscillator whose oscillation frequency is controlled according to the output voltage level of this low-pass filter and which generates a reference clock, and a pseudo-horizontal synchronization signal of 1H period during the vertical blanking period of the video signal as the reference for the analog switch. A PLL circuit comprising: a selection circuit that uses a composite synchronization signal obtained from the video signal as a reference synchronization signal for the analog switch outside a vertical blanking period of the video signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11042190U JPH0466876U (en) | 1990-10-22 | 1990-10-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11042190U JPH0466876U (en) | 1990-10-22 | 1990-10-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0466876U true JPH0466876U (en) | 1992-06-12 |
Family
ID=31857757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11042190U Pending JPH0466876U (en) | 1990-10-22 | 1990-10-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0466876U (en) |
-
1990
- 1990-10-22 JP JP11042190U patent/JPH0466876U/ja active Pending