JPH0417367A - Integrated circuit - Google Patents

Abstract

PURPOSE:To reduce cell areas to minimize the wiring distance from a clock driver to other blocks by placing a cell dedicated to the clock driver in a central portion of a chip. CONSTITUTION:A cell array 2-1 consists, for example, of 7 unit cells 1-1 to 1-7. Similar arrays 2-1, 2-4, and 2-5 are arranged together with the array 2-1. A cell array 2-3 having a cell 3-1 dedicated to a clock driver is placed in a central portion of the arrangement of cell arrays.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device formed by a gate array method.

[Conventional technology]

Conventionally, in this type of semiconductor integrated circuit device, a standardized cell area is set in advance on the base of the gate array. For example, as shown in FIG. 3, a cell array 8-1 having the same cell configuration as a cell array 8-1 in which a plurality of basic cells 7-1 to 7-7 are arranged in one dimension.
2 to 7 are arranged in a two-dimensional direction. Therefore, when forming a block with large driving capacity such as a clock driver, wiring 9 for connecting transistors in parallel is required.
-1 was required. Additionally, the clock driver could be placed anywhere on the chip.

[Problem that the invention attempts to solve]

In the semiconductor integrated circuit device using the conventional gate array method described above, when forming a clock driver, transistors had to be connected in parallel, which resulted in an increase in the area of the constituent cells and a reduction in the wiring area. Ta.

In addition, when the clock driver is placed at an arbitrary position on the chip, the distance from other chips is uniform, resulting in a short distance.

[Means to solve the problem]

The semiconductor device of the present invention is a gate array type semiconductor integrated circuit device in which a plurality of basic cells constituting logic are arranged in an array in one or two dimensions. It is composed of cells.

[Effect]

In the clock driver dedicated cell, the distance between the source and drain of the transistor is larger than that of other cells, so there is no need to connect transistors in parallel as in the conventional case.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram of basic cells in one embodiment of the present invention. As shown in FIG. 1, in this embodiment, a cell array 2 is formed by seven unit cells 1-1 to 1-7.
-1, cell array 2-2, 4.5 formed similarly to cell array 2-1, and cell array 2-3 having p rough driver dedicated cells 3-1 in the center of the cell array. As is clear from FIG. 1, in the clock driver dedicated cell, there is no need to connect transistors in parallel, so the area of the clock driver is minimized. Also, since it is located in the center of the chip, it is easy to make the distance from other cells uniform.

Example 2 shows a case where no clock driver is used on the circuit. In this embodiment, a cell array 5-1 is formed by seven unit cells 4-1 to 4-7, and a cell array 5-2 is formed similarly to the cell array 5-1.
．． 4.5 and a cell array 5 including a wiring dedicated area 6-1 with the same area as the clock driver dedicated cell in the center of the cell array.
~3 are arranged. If a clock driver is not used, the area is located in the center of the chip and can be used as is as a wiring area.

〔Effect of the invention〕

As described above, the present invention has the effect that the area of the constituent cells can be reduced by configuring the cell region to include a cell dedicated to a clock driver in a region near the center.

Furthermore, since it is placed near the center, wiring from the clock driver to other blocks can be minimized, and it has the effect that it can be used as a wiring area even when no clock driver is used.

[Brief explanation of drawings]

1 and 2 are cell layout diagrams in one embodiment of the present invention, and FIG. 3 is a cell layout diagram in a conventional semiconductor integrated circuit device. 1-1~7.4-1~7.7-1~7...mark/basic cell, 2-1~5.5-1~5.8-1~5...group/cell array, 3-1・・・・・・Clock driver dedicated cell,
6-1... Wiring dedicated area, 9-1~2...
··wiring. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] Multiple basic cells constituting logic are arranged in one-dimensional direction or two-dimensional direction.
1. A semiconductor integrated circuit device of a gate array type that is arranged in an array in a dimensional direction, characterized in that a cell dedicated to a clock driver is provided in the center of the chip.