JPH0420156U - - Google Patents
Info
- Publication number
- JPH0420156U JPH0420156U JP5870390U JP5870390U JPH0420156U JP H0420156 U JPH0420156 U JP H0420156U JP 5870390 U JP5870390 U JP 5870390U JP 5870390 U JP5870390 U JP 5870390U JP H0420156 U JPH0420156 U JP H0420156U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- cpu
- controller
- shared
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 12
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Description
第１図は本考案の一実施例の構成図である。
１……ＣＰＵ装置、２……ＣＰＵ、３……固有
メモリ、４……ＤＭＡコントローラ、５……共有
メモリ。
FIG. 1 is a block diagram of an embodiment of the present invention. 1...CPU device, 2...CPU, 3...Specific memory, 4...DMA controller, 5...Shared memory.
Claims (1)
前記ＣＰＵによつて制御され前記固有メモリと前
記共有メモリとにコントロール信号を送り、前記
固有メモリと前記共有メモリとの間でデータをダ
イレクトメモリアクセスにより転送させるＤＭＡ
コントローラを含むＣＰＵ装置を複数組具備し、 前記共有メモリは前記ＣＰＵ装置のすべてのＤ
ＭＡコントローラ、固有メモリに接続され、前記
ＤＭＡコントローラからのコントロール信号によ
り前記固有メモリとの間でデータを転送しあうよ
うにしたことを特徴とするデータ送受信装置。 ２ 前記ＣＰＵ装置が２組であることを特徴とす
る請求項１記載のデータ送受信装置。[Claims for Utility Model Registration] 1. A set of shared memories, a CPU, a unique memory connected to the CPU,
DMA that is controlled by the CPU and sends a control signal to the specific memory and the shared memory to transfer data between the specific memory and the shared memory by direct memory access;
A plurality of sets of CPU devices including a controller are provided, and the shared memory includes all D
A data transmitting/receiving device, characterized in that it is connected to an MA controller and a private memory, and is configured to transfer data to and from the private memory in response to a control signal from the DMA controller. 2. The data transmitting/receiving device according to claim 1, wherein there are two sets of the CPU devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5870390U JPH0420156U (en) | 1990-06-01 | 1990-06-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5870390U JPH0420156U (en) | 1990-06-01 | 1990-06-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0420156U true JPH0420156U (en) | 1992-02-20 |
Family
ID=31584557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5870390U Pending JPH0420156U (en) | 1990-06-01 | 1990-06-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0420156U (en) |
-
1990
- 1990-06-01 JP JP5870390U patent/JPH0420156U/ja active Pending