JPH0420171A - Picture reading device - Google Patents

Abstract

PURPOSE:To reduce the number of parts, to reduce occupancy space and to miniaturize a system by storing the black and white reference level data of respective picture elements with their storing addresses different in one reference level memory in a memory control circuit. CONSTITUTION:A reference level memory 3 stores black and white reference level data in respective picture elements 1a in advance. A memory control circuit 4 makes the black and white reference level data in the respective picture elements 1a with their storing addresses different stored in the reference level memory 3 and makes the black and white reference level data in the respective picture elements 1a outputted in order from the reference level data 3 on shading correcting processing. Then, a shading correcting circuit 2 executes shading correcting based on picture element data outputted from the respective picture elements 1a and the black and white reference level data and prepares a picture element signal. The black and white reference level data are stored in the one memory 3 in this way. Thus, the number of parts can reduced and occupancy space can be reduced and the system can be miniaturized.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an image reading device, and more specifically, to a method for storing reference level data in a memory necessary for performing shading correction processing for creating a pixel signal from pixel data. By storing the white reference level data in one memory, the number of parts can be reduced and the space occupied can be reduced, thereby making the system more compact. The present invention includes a reference level memory that stores different levels, and a memory control circuit that sequentially outputs black and white reference level data for each pixel during shading correction processing.

[Industrial Field of Application] The present invention relates to an image reading device, and more particularly, to a method for storing reference level data necessary for performing shading correction processing to create a pixel signal from pixel data in a memory. .

In an image reading device, in order to perform shading correction processing on pixel data from a light sensing sensor in which light receiving elements constituting pixels are arranged, black and white reference level data for each pixel is stored in memory in advance. The pixel data for each pixel must be stored and processed along with the black and white reference level data for that pixel when creating the pixel signal. Note that the black reference level data is data for each pixel when the light source is turned off, and the white reference level data is data when the light source is turned on and is the whitest.

[Prior Art] Conventionally, black reference level data and white reference level data used in shading correction processing to create a pixel signal from pixel data of each pixel are stored at the same address in separate memories. When an arbitrary address is specified by the address controller when processing pixel data, black reference level data and white reference level data corresponding to the address are simultaneously read out from both memories.

Then, when the white reference level data is W, the black reference level data is B, and the pixel data is S, the shading correction result Q is obtained using the following formula [Problem to be solved by the invention] However, the above conventional In the image reading device described above, two memories were provided to store black and white reference level data for each pixel, which resulted in problems such as an increase in the number of parts and a large space occupied in the system.

The present invention has been made to solve the above problems, and its purpose is to reduce the number of parts and reduce the occupied space by storing black and white reference level data in one memory. An object of the present invention is to provide an image reading device that can be downsized.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

The reference level memory 3 stores black and white reference level data for each pixel 1a in advance.

The memory control circuit 4 stores the black and white reference level data for each pixel 1a in the reference level memory 3 at different storage addresses, and stores the black and white reference level data for each pixel 1a from the reference level memory 3 during shading correction processing. Output data sequentially.

The shading correction circuit 2 performs shading correction based on pixel data output from each pixel 1a and black and white reference level data to create a pixel signal.

[Function] The memory control circuit 4 stores the black and white reference level data in each pixel 1a at different storage addresses.
Since the reference level memory 3 is stored in one reference level memory 3, the number of parts is reduced and the system can be made smaller.

[Embodiment] An embodiment of an image reading device embodying the present invention will be described below with reference to FIGS. 2 to 6.

In FIG. 2, the image sensor 1 is a photosensitive sensor in which a large number of light-receiving elements, such as amorphous sensors, forming a pixel 1a are arranged in a row, and the pixel data Vin of each pixel 1a is input to the sensor 1. Based on the control clock signal CLK, the signals are sequentially and sequentially output as shown in FIG. Each pixel data SO, S of pixel data Vin
l, S2°, . . . respectively include a low-level bright level portion and a high-level dark level portion that are proportional to the amount of incident light.

The A/D converter 11 is connected to each pixel 1a of the image sensor 1.
The pixel data So, Sl, S2°, . . . are converted from analog values to digital values in synchronization with the control clock signal CLK. A shading correction circuit 12 is connected to the A/D converter 11, and the A/D converted pixel data S
O, St.

S2. ... is output to the shading correction circuit 12.

The reference level memory 13 consists of a RAM, and stores black reference level data B and white reference level data W for each pixel 1a.
have sufficient storage capacity to store. For example, if the image sensor l is composed of 1024 pixels 1a, it is preferable to use a reference level memory with a storage capacity of 2048 bytes. The reference level memory 13 is connected to a switching circuit 15 connected to the data bus 14.
It is switched and connected to the A/D converter 11 and the shading correction circuit 12 via.

That is, the timing generator 16 is connected to the switching circuit 15, and outputs the timing control signal TCI to switch the switching circuit 15 to A when the image reading apparatus is powered on, when a processing mode is set from the outside, and at other times when necessary. /D converter 11 side, and connect reference level memory 13 to A/D converter 11. Also, the timing generator 16
After the power is turned on, the timing control signal TC1 is activated at the point in time when the black and white reference level data for all the pixels constituting the image sensor 1 are stored in the reference level memory 13.
output is stopped, the switching circuit 15 is switched to the shading correction circuit 12 side, and the reference level memory 13 is connected to the shading correction circuit 12.

An address controller 17 serving as a memory control circuit is connected to the reference level memory 13 via an address bus 18, and receives a timing control signal TC2 or Te3 from the timing generator 16. Then, the address controller 17 turns off the light source in each pixel 1a of the image sensor 1 during the period when the timing control signal TCI is output from the timing generator 16 and the reference level memory 13 is connected to the A/D converter 11. The pixel data when the light source is turned on in each pixel 1a is stored in the reference level memory 13 as the white reference level data.

That is, when storing the black reference level data in each pixel 1a of the image sensor 1 in the reference level memory 13, the data is stored based on the timing control signal TC2 input at the same period as the control clock signal CLK, as shown in FIG. An address signal.

An+2. An+4. ...a, A2n+1 is sequentially changed and output via the address bus 18, and an L level read/write control signal WE is output at the same period as the same signal CLK, and the A/D converter 11 in each pixel cycle Conversion data B-1゜BO, Bl,
. . , Bn, etc. are stored as shown in FIG.

Furthermore, when storing the white reference level data in each pixel 1a in the reference level memory 13, the address signal is input based on the timing control signal TC2 input at the same period as the control clock signal CLK, as shown in FIG. An
+1. An+3°A n +5. ..., A
2n+2 and output via the address bus 18, and the read/write control signal WE
A/D converter 11 in each pixel cycle
Conversion data W-1, WO, Wl, ... -, Wn
etc. are stored as shown in FIG. Therefore, as shown in FIG. 3, black and white reference level data B and W for each pixel 1a are stored alternately on the reference level memory 13.

Further, in a state where the output of the timing control signal TCI is stopped and the reference level memory 13 is connected to the shading correction circuit 12, the address controller 17 controls each pixel 1a stored in the reference level memory 13.
Black and white reference level data B and W are sequentially read out and output to the shading correction circuit 12.

That is, as shown in FIG.
The address signal is An based on the timing control signal TC3 inputted at a cycle of 1/1.

Anll, An+2. -- ++, A2n-1,
A2n↓2 is sequentially changed and output via the address bus 18, and black reference level data B and white reference level data W are sequentially read from the reference level memory 13 and sent to the shading correction circuit 12 via the data bus 14. Output.

Next, the shading correction circuit 12 will be explained.

A flip-flop (
(hereinafter simply referred to as F/F) 19 is the A/D converter 11
The A/D converted pixel data S at that time is set in synchronization with the timing control signal TC4 output from the timing generator 16 at a constant cycle, and is output as the F/F output shown in FIG. The signal is output to the first subtractor 22.

Each pixel 1 read out from the reference level memory 13 is connected to a delay circuit 20 as a second timing adjustment means.
The black reference level data B at each pixel 1a is sequentially inputted to the delay circuit 2I as a third timing adjustment means, and the white reference level data B at each pixel 1a read from the reference level memory 13 is inputted sequentially. W is input sequentially. Delay circuit 2
0.21 is composed of, for example, a flip-flop, and is configured to receive timing control signals TC5 and TC6 synchronized with the timing control signal TC4 from the timing generator 16.

In each delay circuit 20.21, white and black reference level data B, W for the pixel that outputs each pixel data S set in the F/F 19 is set in synchronization with these control signals TC5, 7C6. , as shown in FIG. 6, are outputted to the second subtracter 23 as an output signal BREG1°WREG synchronized with the output signal of the F/F 19, respectively. Further, the output signal BREGI of the delay circuit 20 is also output to the first subtracter 22.

Then, the first subtracter 22 calculates the difference between the output signal of the F/F 19 and the output signal BREG1 of the delay circuit 20,
The subtraction result is output to the divider 24. Further, the second subtracter 23 receives the output signal WREG of the delay circuit 21゜20,
The difference in BREGI is determined and the subtraction result is output to the divider 24. The divider 24 includes first and second subtracters 22 and 23.
A quotient is determined based on the subtraction result, and the quotient is output as a pixel signal.

In this way, in this embodiment, the black reference level data B at each pixel 1a used for shading correction processing is
Since the white reference level data W and white reference level data W are stored in one reference level memory 13 in advance by sequentially increasing the storage address, the number of parts (number of memories) can be reduced, thereby reducing the occupied space and downsizing the system. can be achieved.

In this embodiment, the reference level memory 13 and the A/D converter 11 are connected and used for shading correction processing when the image reading device is powered on, when the processing mode is set from the outside, and at other times when necessary. Since black reference level data B and white reference level data W are generated for each pixel 1a, suitable white reference level data W can be generated even if the brightness decreases due to long-term use of the light source. shading correction processing can be performed.

Note that in this embodiment, when generating the black reference level data B and the white reference level data W for each pixel 1a, each pixel 1a is
The converted data at each pixel 1a is collected only once and used as black or white reference level data, but the converted data at each pixel 1a is collected multiple times and the average value of these data is adopted as black or white reference level data. You can do it like this.

Further, in this embodiment, the black and white reference level data B and W for each pixel 1a are alternately stored in the reference level memory 13, but the reference level memory 13 is divided into upper and lower parts, and, for example, each pixel 1a The black reference level data for each pixel 1a may be stored in the upper part, and the white reference level data in each pixel 1a may be stored in the lower part.

Furthermore, in this embodiment, the black reference level data B and the white reference level data W for each pixel 1a used for shading correction processing are generated when the image reading device is powered on, or the black reference level data B and white reference level data W are stored in the reference level memory 13 in advance. Predetermined black and white reference level data may be stored.

Further, in this embodiment, the light sensing sensor is described as an amorphous sensor, but the present invention is not limited to this.

[Effects of the Invention] As detailed above, according to the present invention, by storing black and white reference level data in one memory, it is possible to reduce the number of parts, reduce the space required, and downsize the system. It has an excellent effect in that it can achieve the following.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is an electrical block circuit diagram showing an embodiment of the invention, Fig. 3 is a diagram showing a reference level memory, and Fig. 4 shows writing of reference level data. FIG. 5 is a waveform diagram showing writing of reference level data, and FIG. 6 is a waveform diagram illustrating creation of a pixel signal. In the figure, 1 is a photo-sensing sensor, 1a is a pixel, 2 is a shading correction circuit, 3 is a reference level memory, 4 is a memory control circuit, 19 is a flip-flop as a first timing adjustment means, 20 is a second timing 21 is a delay circuit as a third timing adjustment means; 2 is a first subtracter; 3 is a second subtractor; 4 is a divider.

Claims (1)

[Claims] 1. Black and white standards for each pixel (1a) for each pixel data output from a photosensitive sensor (1) in which multiple rows of light receiving elements constituting the pixel (1a) are arranged. In an image reading device equipped with a shading correction circuit (2) that performs shading correction based on level data and creates a pixel signal, black and white reference level data for each pixel (1a) are stored at different storage addresses. An image reading device comprising: a reference level memory (3); and a memory control circuit (4) that sequentially outputs black and white reference level data for each pixel (1a) during shading correction processing. 2. The memory control circuit (4) stores black and main reference level data in each pixel (1a) in the reference level memory (3) at different storage addresses. Item 1. Image reading device according to item 1. 3. The shading correction circuit is configured to adjust each pixel (1a
), first to third timing adjustment means (19
~21), a first subtracter (22) for calculating the difference between the output signals of the first and second timing adjustment means (19, 20), and second and third timing adjustment means (20, 21) a second subtractor (23) that calculates the difference between the output signals of , and a divider (23) that calculates a quotient based on the subtraction results of the first and second subtracters (22, 23) and outputs it as a pixel signal.
24). The image reading device according to claim 1, further comprising: