JPH04206832A - Formation of ohmic electrode - Google Patents

Abstract

PURPOSE:To sufficiently reduce base parasitic resistance, by selectively forming a base electrode only in a base region by nonelectrolytic plating, and forming a lower resistive electrode on an emitter electrode. CONSTITUTION:A collector layer 2, a base layer 3, and an emitter layer 4 are epitaxially grown in order on a compound semiconductor substrate 1. An emitter electrode, e.g. a WSi layer 5 is formed on the layer 4. An insulating film 6 is worked in the shape of an emitter electrode pattern on the layer 5. By using the insulating film 6 as a mask, the WSi layer 5 is etched, and further the emitter later 4 also is etched. An insulating film sidewall 7 is formed on their sidewall. A base electrode 10 is selectively formed in a base region by nonelectrolytic plating, e.g. nonelectrolytic plating of Ni. By a bias electron cycrotron resonance CVD method, a flattened insulating film 11 is formed. The WSi electrode 5 is exposed from the insulating film 11 by etch back. Low resistance metal, e.g. Au/Mo 12 is stacked and formed on the WSi electrode 5 by evaporation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming an ohmic electrode in a compound semiconductor device, particularly.

[Conventional technology]

Figure 3 shows HB T (Hetero Bipolar
Transistor Hetero Bipolar Transistor)
FIG. 2 is a cross-sectional view showing the manufacturing process of a conventional method for forming a Heath electrode. Next, the manufacturing process will be explained step by step.

First, as shown in Figure 3 (al), a compound semiconductor substrate (1
), the collector layer (2), the base layer (3) and the emitter layer (
4) is epitaxially grown, an emitter electrode, for example, a WSi layer (5) is formed thereon, and an insulating film (6) is further formed into an emitter electrode pattern thereon. Next (as shown in figure b1), using the insulating film (6) as a mask, the WSi layer (
5), and also the emitter layer (4). Subsequently, an insulating film (7) is formed on those side walls.

Next, a base electrode (8) is deposited as shown in (C). Then, as shown in Figure (d), after flattening with a resist (9), etching is carried out by Ar ion milling or the like to remove the base electrode in two parts of the emitter electrode. Furthermore, as shown in Figure (e), the base electrode on the side wall of the emitter electrode is also etched away by oblique ion milling.

Through the above steps, the base electrode (8) is formed in a self-aligned manner with respect to the emitter electrode (5).

[Problem to be solved by the invention]

In the conventional base electrode formation method, the emitter electrode and the base electrode cannot be separated unless the base electrode on the upper part of the emitter electrode is removed by etchback and then the base electrode on the side wall of the emitter electrode is removed by diagonal ion milling. I can't do it.

However, it is difficult to remove only the sidewall part of the base electrode with oblique ion milling compared to the flat part of the base electrode, and there is a problem that the process lacks stability. In order to make it easier to form, it is effective to make the emitter electrode thicker, but there is also a problem that there is a limit to the reduction of the emino parasitic resistance.

This invention was made to solve the above problems, and it is possible to form a base electrode in a self-aligned manner with respect to an emitter electrode without using an unstable process such as oblique ion milling. The object of the present invention is to obtain a method for forming an ohmic electrode in which parasitic resistance of an emitter electrode and a base electrode is reduced as much as possible.

[Means to solve the problem]

In the method for forming an ohmic electrode according to the present invention, since the base electrode is selectively formed only in the base region by electroless plating, there is no need to perform oblique ion milling. In addition, by forming a lower resistance electrode on the emitter electrode, we reduced the emitter parasitic resistance, and by using this upper layer electrode as a mask, we decided to form the lead wiring for the base electrode. Even when a plated metal having a higher specific resistance than metal is used, the base parasitic resistance can be sufficiently reduced.

[Effect]

In the method of forming the ohmink electrode in this invention, the base electrode is selectively grown by electroless plating.
It can be formed in a self-aligned manner with respect to the emitter electrode, and
We decided to form a low-resistance electrode on top of the emitter electrode, and then use this electrode as a mask to form a low-resistance wiring on the heath electrode as well, thereby reducing the parasitic resistance of the emitter and heath. can.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
Figures (a) to (i) are cross-sectional views showing manufacturing steps of a method for forming an ohmic electrode according to an embodiment of the present invention. The manufacturing process of HBT will be taken as an example, similar to the conventional one, but this is an example of the manufacturing process of R
HE T (Resonant Hot Electro
n Transistor (Resonant hot electron transistor), RB T (Resonant B
Needless to say, the present invention can be similarly applied to a resonant bipolar transistor (ipolar transistor), etc.

First, as shown in FIG. 1(a), a compound semiconductor substrate (1
), a collector layer (2), a base layer (3), and an emitter layer (4) are epitaxially grown in sequence, an emitter electrode such as a W Si layer (5) is formed on top of this, and an insulating film is further formed on top of that. (6) is processed into an emitter electrode pattern shape. Next, (1) as shown in the figure, the WSi layer (5) is etched using the insulating film (6) as a mask, and the emitter layer (4) is also etched. Subsequently, insulating film sidewalls (7) are formed on those sidewalls. Next, as shown in the figure (C), a base electrode 00) is selectively formed on the base region by electroless plating, for example, electroless plating of Ni. next(
d) Biased electron cyclotron resonance CV as shown
A flattened insulating film (1υ) is formed by D (hereinafter referred to as bias ECR-CVD) method. Then, as shown in the figure (e), the WSi electrode (5) is etched back to form an insulating film (1υ).
Expose from 1υ. Furthermore, as shown in FIG. 3(f), a low resistance metal such as Au/MoQa is formed over the WSi electrode (5) by vapor deposition. Next, as shown in the figure (g), the insulating film (11) is removed by anisotropic etching using the low resistance metal (12 as a mask.
1) Add an undercut by isotropic etching.

Finally, (i) As shown in the figure, the base electrode wiring example is Au/
Mo/Ti (deposit bone).

Figure 2(a) shows the base electrode (13) when only electroless plated metal is used, and Figure 2(b) shows the emitter electrode (5).
2(C) is a cross-sectional view comparing the case of this example, in which a low resistance electrode is stacked on top of the base electrode and a base electrode is deposited using this as a mask.

In the case of only electroless plating as shown in the figure (a), there is a drawback that the resistance of the metal is higher than that of vapor-deposited metal.

(1)) In the case of the figure, the emitter electrode (5) and the base electrode (
There is a limit to how much it can be reduced because it is determined by the distance between expensive.

However, in the case of this embodiment, the drawbacks shown in FIGS. (a) and (b) are eliminated by forming the base metal by plating and by overlapping the wiring on the base.

〔Effect of the invention〕

As described above, according to the present invention, since the base metal is selectively formed in the base region by electroless plating, the base electrode can be formed in a self-aligned manner even with respect to the fine emitter electrode. It is advantageous for miniaturization and, by extension, speedup. Moreover, since both the emitter and base electrodes are layered with low-resistance metal wiring, parasitic resistance is sufficiently reduced, and furthermore, it is advantageous for speedup of element j'-. There is an effect that it is.

[Brief explanation of the drawing]

Figures 1(a) to (]) show an HB which is an embodiment of the present invention.
1 New view showing the manufacturing process of T, Figure 2. Figure 3 (a, j
-(e) are cross-sectional views showing the manufacturing process of a conventional HBT. In the figure, (1) is a compound semiconductor substrate, (2) is a collector layer, (3) is a base layer, (4) is an emitter layer, and (5) is a collector layer.
) is the WSi emitter electrode, (6) is the insulating film, (7) is the insulating film sidewall, C0) is the electroless plated metal, (
1υ is an ECR-CVD flattened insulating film, C2 is an emitter wiring, and (13 is a base wiring. In the figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In a compound semiconductor device consisting of at least two or more types of semiconductor layers, when forming an ohmic electrode on the second semiconductor layer in a self-aligned manner with respect to the electrode formed on the uppermost semiconductor layer, it is necessary to A first step of processing and forming an electrode pattern on the uppermost semiconductor layer using an insulating film as a mask for a compound semiconductor substrate having a semiconductor layer formed on its surface.
a second step of etching away the uppermost semiconductor layer using the insulating film/electrode pattern as a mask to form a sidewall of the insulating film; and a second step of forming an ohmic layer on the exposed surface of the second semiconductor layer by electroless plating. a third step of forming an electrode; a fourth step of exposing the electrode on the uppermost semiconductor layer from the insulating film by forming, flattening and etching back an insulating film; and forming an electrode on the uppermost semiconductor layer by photolithography. An electrode is further formed on the upper electrode, the insulating film is etched away using this electrode as a mask, and the exposed plating electrode is also deposited by vapor deposition using the electrode on the uppermost semiconductor layer as a mask. A method for forming an ohmic electrode, comprising a fifth step of forming an electrode.