JPH04214672A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which has reduced junction leak current in a drain region and to provide the method for manufacturing thereof. CONSTITUTION:About a gate insulated film, the thickness of a region on the drain side is larger than that of a region on the source side. The thin part is constituted of a first gate insulated film 3 and a first gate electrode 4 is formed on the thin part. The thick part is constituted of the first gate insulated film 3 and a second gate insulated film 9 and a second gate electrode 11 is formed on the thick part. Consequently, even if a large voltage is applied between a source and a drain, the electric field intensity in a junction part of a drain region is alleviated and thus a junction leak current is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a transistor and driver for driving picture elements of a liquid crystal display device, and a static RAM (SRAM).
), etc., and a method for manufacturing the same.

0002

[Prior art] Conventional thin film transistor element (TFT)
A cross section of is schematically shown in FIG. 2(e). This TFT is
A semiconductor layer (polycrystalline silicon layer) 22 provided on an insulating substrate 21 , a source region 25 a and a drain region 25 b formed on the semiconductor layer 22 and made up of impurity diffusion regions, and a gate formed on the semiconductor layer 22 Insulating film (SiO2
23 and a gate electrode 24 formed on the gate insulating film 23. The source region 25a and the drain region 25b are each formed in regions located on both sides of the gate electrode 24 in the semiconductor layer 22. An interlayer insulating film 26 covers these, and a contact hole 27 is opened in the interlayer insulating film 26. The source region 25a and the drain region 25b are connected through the contact hole 27.
An Al--Si wiring 28 is formed on the interlayer insulating film 26 so as to be in contact with the interlayer insulating film 26.

[0003] Hereinafter, a method for manufacturing the above TFT will be explained with reference to FIGS. 2(a) to 2(e).

First, a semiconductor layer 22 is formed on an insulating substrate 21 (FIG. 2(a)), and then a gate insulating film 23 is formed on the insulating substrate 21 by CVD so as to cover the semiconductor layer 22.
1 (FIG. 2(b)). Furthermore, after the gate insulating film 23 is formed, a gate electrode 24 made of polycrystalline silicon is formed on the gate insulating film 23 (FIG. 2(b)).
).

After the gate electrode 24 is formed, impurities are injected into the semiconductor layer 22 by ion implantation using the gate electrode 24 as a mask, and an impurity implantation region is formed in a self-aligned manner (see FIG. 2(c)). )). As for the implantation conditions, for example, phosphorus (P) is used as an impurity, acceleration energy is 50k,
The conditions for implantation at eV and dose of 2×10 15 cm −2 are selected.

After the interlayer insulating film 26 is deposited, an annealing process is performed at 950° C. for 30 minutes in a nitrogen atmosphere to activate impurities. By this annealing, the impurity implanted regions are formed into the source region 25a and drain region 2 of the TFT.
5b (Fig. 2(d)). After the contact hole 27 is formed in the interlayer insulating film 26, an Al--Si wiring 28 is formed as shown in FIG. 2(e).

[0007]

However, the above-mentioned prior art has the following problems.

In the above TFT, the voltage between the source region 25a and the drain region 25b (source-drain voltage) and the reverse voltage between the gate electrode 24 and the source region 25a (gate-source reverse voltage) When the pn junction is increased, the strength of the drain electric field at the pn junction formed in the drain region 25b increases, resulting in an increase in junction leakage current at that part.

Generally, the source region, channel region, and drain region of a TFT are formed in a semiconductor layer deposited on an insulating substrate or in a semiconductor layer formed on an insulating layer on a semiconductor substrate. . Therefore, the crystallinity of the semiconductor layer is inferior to that of the single crystal semiconductor substrate. Therefore, in TFTs, the problem of junction leakage in the drain region is more important than in bulk MOS transistors. In particular, when a TFT is used as a driving element of a liquid crystal display device, it is required to operate at a higher voltage than a normal LSI, so the influence of junction leakage on transistor characteristics becomes greater.

The present invention has been made to solve the above-mentioned problems, and its purpose is to prevent the junction portion of the drain region from being damaged even when a large voltage is applied between the source and the drain and between the gate and the source. An object of the present invention is to provide a semiconductor device in which the electric field strength at the junction is relaxed, thereby reducing the junction leakage current at that part.

Another object of the present invention is to provide a manufacturing method that can easily manufacture a semiconductor device in which the electric field strength at the junction portion of the drain region is relaxed, thereby reducing the junction leakage current at that portion. .

0012

[Means for Solving the Problems] A semiconductor device of the present invention includes:
A semiconductor layer, a source region and a drain region made of an impurity diffusion region formed in the semiconductor layer, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film. A semiconductor device having a gate insulating film sandwiched between the semiconductor layer and the gate electrode, the region on the side where the drain region is located is larger than the region on the side where the source region is located. It has a thick structure,
Thereby, the above objective can be achieved.

Further, the region of the gate insulating film on the side where the source region is located has a first gate insulating film portion,
The region of the gate insulating film on the side where the drain region is located has the first gate insulating film portion and a second gate insulating film portion formed on the first gate insulating film portion, and The electrode may have a first gate electrode portion formed on the first gate insulating film portion and a second gate electrode portion formed on the second gate insulating film portion.

The manufacturing method of the present invention is a method for manufacturing a semiconductor device having a semiconductor layer and a source region and a drain region made of impurity diffusion regions formed in the semiconductor layer, forming a first gate insulating film on the first gate insulating film; forming a first gate electrode on the first gate insulating film; and forming a second gate insulating film on the first gate insulating film. , forming a second gate electrode on the second gate insulating film; using the first gate electrode and the second gate electrode as masks, forming the source region and the drain region in the semiconductor layer in a self-aligned manner; The above objective can be achieved by this process.

[0015]

[Example] Figure 1(d) shows a TFT which is an example of the present invention.
The cross section of the figure is schematically shown.

This TFT has a semiconductor layer (layer thickness: about 100 nm) 2 formed on an insulating substrate 1. Furthermore, this TFT includes a source region 5a and a drain region 5b, which are formed in the semiconductor layer 2 and are made up of impurity diffusion regions;
A first gate insulating film (film thickness, approximately 50 nm) 3 formed on the semiconductor layer 2, a first gate electrode 4 formed on the first gate insulating film 3, and a first gate insulating film 3 formed on the first gate insulating film 3. The second gate insulating film 9 has a second gate insulating film (thickness: approximately 150 nm) and a second gate electrode 11 formed on the second gate insulating film 9.

The source region 5a is formed in the semiconductor layer 2 on the side on which the second gate electrode 11 is not provided, out of both sides of the first gate electrode 4. The drain region 5b is the first
It is formed in the semiconductor layer 2 on the side where the second gate electrode 4 is provided on both sides of the gate electrode 11 .

As described above, in the TFT of this embodiment, in the portion of the gate insulating film sandwiched between the semiconductor layer 2 and the gate electrodes 4 and 11, the gate insulating film 3 and the gate insulating film on the drain region 5b side are 9 is the gate insulating film 3 on the source region 5a side.
It has a thicker structure. Therefore, even if a large voltage is applied between the source and the drain and between the gate and the source during operation of the transistor, the electric field strength at the junction of the drain region 5b is relaxed. As a result, leakage current generated at the junction of drain region 5b is reduced.

When the TFT of this embodiment is used, for example, as a picture element driving element of a liquid crystal display device, the thickness of the first gate insulating film 3 is preferably in the range of 50 nm to 100 nm. Further, the thickness of the second gate insulating film 9 is preferably in the range of 100 nm to 150 nm.

FIGS. 1(a) to 1(d) schematically show cross sections of a TFT in each main step of a manufacturing method according to an embodiment of the present invention. Hereinafter, a method for manufacturing the above TFT will be explained with reference to FIGS. 1(a) to 1(d).

First, a semiconductor layer 2 was formed on an insulating substrate (hereinafter referred to as a substrate) 1, and then a first gate insulating film 3 was formed on the substrate 1 so as to cover the semiconductor layer 2 (see FIG. 1).
(a)).

In this example, a silicon layer was deposited as the semiconductor layer 2 by the CVD method. However, as the semiconductor layer 2, a layer made of another semiconductor, such as a compound semiconductor, may be used. Further, the formation method is not limited to the CVD method, and other thin film deposition methods may be used.

In this embodiment, a quartz glass substrate was used as the substrate 1. However, as the substrate 1, a substrate made of another insulating material or a substrate made of a conductive material on which an insulating layer is provided may also be used.

After forming the first gate insulating film 3, a first gate electrode 4 made of polycrystalline silicon is formed by a conventional method.
was formed on the first gate insulating film 3 (FIG. 1(a)). As the material for the first gate electrode 4, polycrystalline silicon, a high melting point metal, or a high melting point metal silicide is preferable from the viewpoint of having a high melting point that can withstand high temperature processes. Further, the structure of the first gate electrode 4 is not limited to a single layer structure made of the above materials, but may be a multilayer structure, for example, a two layer structure (polycide structure) made of a polycrystalline silicon layer and a silicide layer. .

The second gate insulating film 9 is replaced by the first gate insulating film 3.
After the formation, a contact hole 10 was formed in the second gate insulating film 9 on a predetermined region of the first gate electrode 4, as shown in FIG. 1(b).

Next, as shown in FIG. 1(c), the second
A gate electrode 11 was formed on the second gate insulating film 9. The first gate electrode 4 and the second gate electrode 4 are connected through the contact hole 10.
It was in contact with the gate electrode 11 and was electrically connected. Second
The above description regarding the first gate electrode 4 also applies to the material and structure of the gate electrode 11.

According to the above method, it was possible to easily form a gate insulating film having two portions with different thicknesses. Further, a first gate electrode 4 is formed on the thin part (first gate insulating film 3), and a second gate electrode is formed on the thick part (second gate insulating film 9). We were able to form 11.

After forming the second gate electrode 11, impurities are injected into the semiconductor layer 2 by ion implantation using the first gate electrode 4 and the second gate electrode 11 as masks to form an impurity implanted region. (Figure 1(c)). Phosphorus (P) was used as an impurity. In this example, the ion implantation dose was 2×10 15 cm −2 and the acceleration energy was 200 keV.

An interlayer insulating film (thickness: 60 mm) was formed by CVD method.
After depositing 6 (0 nm) 6, an annealing process (950°C, 3
0 minutes, nitrogen atmosphere). Through this annealing process, the impurity implanted regions became the source region 5a and drain region 5b of the TFT (FIG. 1(d)).

In this way, the source region 5a and drain region 5b were formed in self-alignment with the first and second gate electrodes 4 and 11. More specifically, source region 5a was formed in self-alignment with respect to first gate electrode 4, and drain region 5b was formed in self-alignment with respect to second gate electrode 11.

After forming the contact hole 7 in the interlayer insulating film 6, as shown in FIG. 1(d), an Al--Si wiring 8 was formed to fabricate the TFT of this example.

As mentioned above, the semiconductor device of this example has the following features:
Although this is a TFT, the scope of application of the present invention is not limited thereto. For example, the single crystal semiconductor substrate itself may be used as the semiconductor layer 2. In that case, the term "semiconductor layer" in the description of the embodiments will refer to the single crystal semiconductor substrate itself, and the term "TFT" will refer to the bulk type MOS transistor. When a single crystal semiconductor substrate is used as the semiconductor layer 2, a semiconductor layer with excellent crystallinity can be obtained, so the influence of junction leakage is reduced.
smaller than in TFT. Therefore, according to the configuration of the present invention, further miniaturization is possible.

Note that in the above embodiment, the first gate electrode 4 and the second gate electrode 11 are electrically connected, but these gate electrodes 4 and 11 are electrically insulated and separated. It is also possible to adopt a configuration in which different potentials are applied to each.

Since the present invention can provide a small TFT with reduced leakage current, it particularly contributes to the field of driving elements of liquid crystal display devices, which have been rapidly developed in recent years.

[0035]

As described above, according to the semiconductor device of the present invention, the distance between the gate electrode and the drain region is increased compared to the distance between the gate electrode and the source region. The electric field strength at that portion is relaxed, thereby reducing the junction leakage current at that portion.

Furthermore, according to the manufacturing method of the present invention, a structure in which the distance between the gate electrode and the drain region is greater than the distance between the gate electrode and the source region can be easily formed. Therefore, the electric field strength at the junction portion of the drain region is relaxed, thereby easily manufacturing a semiconductor device in which junction leakage current at that portion is reduced.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are cross-sectional views showing embodiments of the present invention.

FIGS. 2(a) to 2(e) are cross-sectional views showing the prior art.

[Explanation of symbols]

1 Insulating substrate 2 Semiconductor layer 3 First gate insulating film 4 First gate electrode 5a Source area 5b Drain region 6 Interlayer insulation film 7 Contact hole 8 Wiring 9 Second gate insulating film 10 Contact hole 11 Second gate electrode

Claims (3)

[Claims] 1. A semiconductor layer; a source region and a drain region each formed of an impurity diffusion region formed in the semiconductor layer;
A semiconductor device comprising a gate insulating film formed on the semiconductor layer and a gate electrode formed on the gate insulating film, the semiconductor device having a gate insulating film formed on the semiconductor layer and the gate electrode. The portion sandwiched between is a semiconductor device in which a region on the side where the drain region is located is thicker than a region on the side where the source region is located. 2. The region of the gate insulating film on the side where the source region is located has a first gate insulating film portion, and the region of the gate insulating film on the side where the drain region is located has a first gate insulating film portion. The gate electrode has a gate insulating film portion and a second gate insulating film portion formed on the first gate insulating film portion, and the gate electrode has a first gate electrode formed on the first gate insulating film portion. 2. The semiconductor device according to claim 1, further comprising a second gate electrode portion formed on the second gate insulating film portion. 3. A method for manufacturing a semiconductor device having a semiconductor layer and a source region and a drain region each formed of an impurity diffusion region formed in the semiconductor layer, the method comprising:
forming a first gate insulating film on the semiconductor layer; forming a first gate electrode on the first gate insulating film; and forming a second gate insulating film on the first gate insulating film. forming a second gate electrode on the second gate insulating film; using the first gate electrode and the second gate electrode as masks, forming the source region and the drain region in the semiconductor layer in a self-aligned manner; 1. A method for manufacturing a semiconductor device, the method comprising: forming a semiconductor device inside the device.