JPH042157A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the warpage of a silicon substrate by applying a silicon nitride film between layers in an integrated circuit or the back of the silicon substrate. CONSTITUTION:An insulating layer 3 of SiO2 for isolation between layers ls formed on an active 2 layer on a silicon substrate 1. A silicon nitride film 4 is deposited on the insulating layer to eliminate the warpage of the silicon substrate. A polysilicon film 5 is deposited on the silicon nitride film 4 to prevent electrical interferences between layers. The polysilicon film is covered with an insulating film for insulation between layers.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a laminated integrated circuit.

While conventional integrated circuits have elements integrated in a plane, conventional integrated circuits are tertiary integrated circuits in which silicon single crystal layers containing elements such as transistors are stacked vertically with an interlayer insulating film in between. This is the original integrated circuit.A feature of such a stacked integrated circuit is that it not only improves the degree of integration, but also enables wiring in the direction between the upper and lower layers.The wiring length is much shorter than that in a plane. The wiring delay time between elements is shortened, and many signals within the same plane can be simultaneously transferred between upper and lower layers, making it suitable for massively parallel processing.

A conventional method for manufacturing a laminated integrated circuit will be described below with reference to FIG. FIG. 3 is a sectional view showing the manufacturing process of a multilayer integrated circuit having a three-layer structure. Figure 3 (a
), 1 is a silicon substrate, and 2A is an active layer formed on the silicon substrate 1. After forming the two active layers, proceed as shown in Figure 3(b) 5i02 to insulate and separate the layers.
Interlayer insulating film 3D with a thickness of about 0.5 μm to 0.7 μm, etc.
Next, a polycrystalline silicon film 5B having a thickness of about 0.5 μm is deposited to prevent electrical interference between layers, and an interlayer insulating film 3E is further formed on the polycrystalline silicon 5B. FIG. 3(c)G;L Polycrystalline or amorphous silicon is formed on the interlayer insulating film 3E, and is crystallized by a beam crystallization method such as laser crystallization or electron beam crystallization to form a single crystal silicon layer. , shows a state in which a second active layer 6A having a thickness of about 0.5 μm is formed.

Thereafter, the third layer can be formed by repeating the steps shown in FIGS. 3(a) to 3(c). Figure 3 (
d)ii Shows the state after formation of the third layer. Here, 3F and 3G are multilayer insulation layers, 5C is polycrystalline silicon A, and 7A is an active layer.

Problems to be Solved by the Invention In a laminated integrated circuit as shown in Figure 3 (for example, insulating polycrystalline silicon traps such as J:, 5i02, laser crystallization or electron beam crystallization) As monocrystalline silicon layers, etc., crystallized by beam crystallization methods such as
By going through multiple thermal processes to form integrated circuits,
Stress accumulates and the silicon substrate warps,
The present invention has been made in view of these problems, and it is possible to manufacture a laminated integrated circuit in which warping of the silicon substrate is not a problem when laminating a large number of integrated circuit layers. According to the present invention ζ, it is an object of the present invention to provide a method for manufacturing a laminated integrated circuit. This is a method for manufacturing a laminated integrated circuit, characterized by depositing a silicon nitride film of .

Effect 4i Causes of warpage of silicon substrate in laminated integrated circuits
A laminated integrated circuit is composed of films with different coefficients of thermal expansion.
Thermal process forces that cause stress (because the number of layers is twice as many as in a normal integrated circuit) The main elements that make up a multilayer integrated circuit are the silicon film and the 5i02 film (the coefficient of thermal expansion of the silicon film is the 5i02 film) This is about 10 times that of the silicon substrate, and this is the main cause of warping of the silicon substrate.Therefore, the internal stress of the substrate has almost the same coefficient of thermal expansion as the silicon film.Difference in the coefficient of thermal expansion between the silicon film and the 5i02 film By depositing a silicon nitride film that acts in the opposite direction of the stress caused by
Embodiment (Embodiment 1) An embodiment of the present invention will be described based on the drawings. Figure 1 ζ friend
This is a cross-sectional view showing the manufacturing process of a three-layer integrated circuit according to the first embodiment of the present invention. In FIG. Even in the case of an active layer, after forming the active layer 2, an interlayer insulating film 3 with a thickness of about 0.5 μm to 0.7 μm, such as 5i02, is formed to insulate and isolate the layers, as shown in FIG. 1(b). Next, as shown in Figure 1(c), a silicon nitride film 4 with a thickness of about 0.1 μm is deposited to reduce the warpage of the silicon substrate.Next Figure 1(d)
As shown in the figure, a polycrystalline silicon film 5 with a thickness of about 0.5 μm is deposited on the silicon nitride film 4 to prevent electrical interference between layers, and an interlayer insulating film 3A is further formed on the polycrystalline silicon 5. Figure 1 (e) IT interlayer insulating film 3
Form polycrystalline or amorphous silicon on A
This shows a state in which a single crystal silicon layer is formed by crystallization by a beam crystallization method such as laser crystallization or electron beam crystallization, and a second active layer 6 having a thickness of about 0.5 μm is formed. After that, the third layer can be formed by repeating the steps from Fig. 1(a) to (e). Fig. 3(d) shows the state after the formation of the third layer. It shows. Here, 3B and 3C are interlayer insulation wL4A is silicon nitride i5A is polycrystalline silicon 7 is the third active layer.

Pass! When a three-layer multilayer integrated circuit is formed using a 6-inch silicon substrate, in the conventional method, the silicon substrate warps by a force t of about 200 μm.
By depositing 4.4 A of silicon nitride film between each integrated circuit layer, the warpage of the silicon substrate could be reduced to about 50 μm (Example 2) Next Stacked integration in the second example of the present invention A schematic cross-sectional view of the circuit is shown in FIG. 2. FIG. 2 shows a three-layer stacked integrated circuit similar to that in FIG. 1. 21 is a silicon substrate 22, 23.
, 24 are 1st layer random, 2nd layer giant, 3rd layer active voice 25
26 is a polycrystalline silicon film. 27 is a silicon nitride film deposited on the back surface of the silicon substrate 21 after forming the third active layer 24. By depositing a silicon nitride film with a thickness of 1.5 μm, the warpage of about 200 μm immediately after the formation of the third active layer 24 can be reduced to 30 μm. During manufacturing, by depositing a silicon nitride film on the layer surface of each integrated circuit layer or on the back surface of the silicon substrate, it is possible to significantly reduce the warpage of the silicon substrate, and it is possible to form a multilayer integrated circuit in which a large number of integrated circuit layers are stacked. becomes possible.

[Brief explanation of the drawing]

1st F! ;! J is a schematic cross-sectional view of the process for forming a laminated integrated circuit in the first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the laminated integrated circuit in the second embodiment. It is a schematic process sectional view for. 1... Silicon base & 2, 6,, 7... Active state 3... Interlayer insulation M,, 4... Silicon nitride gourd 5.
...Polycrystalline silicon wind agent's name Patent attorney Shigetaka Awano (1 person) Figure 1 Figure 1 (e) B Active layer Figure 5N 11B Comprehensive view of crystalline silicon film

Claims (2)

[Claims] (1) A method for manufacturing a laminated integrated circuit, characterized in that, in manufacturing the laminated integrated circuit, at least one layer of silicon nitride film is formed between each integrated circuit layer to reduce warpage of the silicon substrate. . (2) A method for manufacturing a laminated integrated circuit, which comprises depositing a silicon nitride film on the back surface of a silicon substrate to reduce warpage of the silicon substrate when manufacturing the laminated integrated circuit.