JPH0423151A - Memory testing system - Google Patents

Abstract

PURPOSE:To simplify a memory test and to shorten the test time by providing a test address generator and a test write data generator and carrying out the memory test of a RAM array within a storage device. CONSTITUTION:A write address generator 16 and a test data generator 17 are provided to a storage device to produce the test addresses and the write data in response to the external test requests. Meanwhile the selectors 21 and 22 perform the switch between the addresses and data produced by both generators 16 and 17 and the addresses and the data given from the external application devices for accesses applied to a RAM array 10 forming a storage part of the storage device in a normal state. Then a memory test is given to the array 10 by means of a check bit generator 14 and an error detection/ correction circuit 15 which are originally owned by the array 10. As a result, a test program is simplified and the test of the storage device is facilitates. Furthermore the test time is also shortened since the array 10 can be tested with in the storage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a memory test method for testing a storage device included in an information processing device.

(Prior Art) Generally, a computer system includes an arithmetic and control unit that serves as the control center of the system, and a main memory that is used to store various programs and data.

This main memory device is composed of a semiconductor memory element (RAM), and its capacity (memory capacity) is increasing year by year due to advances in semiconductor technology and high-density packaging technology.

Conventionally, testing of a main memory device (memory test) has been carried out by using a test program based on a combination of instructions, and having an arithmetic control unit, which forms the core of a computer system, execute this test program.

(Problems to be Solved by the Invention) As described above, in the conventional memory test method, the arithmetic and control unit reads/writes data in the main memory according to a test program. For this reason,
The disadvantage is that the time required for testing (test time) also increases in proportion to the installed capacity of the main memory, which is a particular problem when testing a large capacity main memory.

This invention was made in view of the above circumstances, and its purpose is to provide a memory test method that can easily perform memory tests on storage devices, such as main storage devices, and that can shorten the time required for memory tests (test time). Our goal is to provide the following.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a method in which a test signal for requesting a memory test of a storage device such as a main storage device whose storage section is constituted by a RAM array is sent to the device from outside. A test control circuit that controls a memory test by switching from normal mode to test mode, a test address generator that generates a test address for testing a RAM array, and a test address generator that generates a test address for testing a RAM array. A test data generator that generates test write data, a RAM array control circuit that controls read/write to the RAM array, and a RAM that connects the address given by the device and the test address generated by the test data generator. a first selector for switching as an array address; a second selector for switching between write data provided from a utilization device and test write data generated by a test data generator as data to be written to the RAM array;
A check bit generator generates a check bit for error detection and correction based on the data selected by the second selector in the case of a write access and outputs it to the RAM array, and in the case of a read access. RAM according to the address selected by the first selector.
An error detection/correction function that detects and corrects errors based on the data read from the array and the check bits of the same data.
It is equipped with a correction circuit and a status holding means that holds error status information including the address at that time when an error is detected by the error detection/correction circuit, and the storage device internally stores the error status information including the address at that time when an error is detected by the error detection and correction circuit. This system is characterized in that it performs a memory test of the RAM array.

(Operation) According to the present invention, when a test signal is applied to a storage device such as a main storage device from the outside, the RA is changed from a normal mode in which an external usage device accesses the storage device to an RA inside the storage device.
The test mode is switched to perform a memory test of the M array. In this test mode, under the control of the test control circuit, the test write address is set to, for example, RA.
A read address is generated from the first address of the M array to the last address, and then a test read address is generated from the first address to the last address of the RAM array. Furthermore, during write access in the test mode, test write data is generated under the control of the test control circuit. In the test mode, the above-described test address and test write data are used in place of the address and data (write data) given from an external device in the normal mode. During write access in test mode, a check bit for test write data (check bit for error detection/correction) is generated by a check bit generator, and the test write data is written to the RAM array according to the specification of the test address. When entering the
The write data is written to the RAM array corresponding to the write data.

When writing in the test mode is performed from the first address to the last address of the RAM array, write access is switched to read access under the control of the test control circuit. When accessing read in test mode,
The data specified by the test address is read out from the RAM array together with the corresponding check bit and subjected to error detection and correction processing by the error detection and correction circuit.

Here, if an error is detected, status information including the test address (error address) at that time is held in the status holding means.

Therefore, the utilization device can grasp the error status of the RAM array of the storage device simply by reading the contents of this status holding means.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a main storage device in a computer system to which the present invention is applied. In the figure, reference numeral 10 constitutes a storage section of the main memory device and is a RAM array to be subjected to a memory test. Reference numeral 11 indicates a test mode in response to a test signal T given from an arithmetic control unit or other control unit (not shown). This is a test control circuit for setting and controlling a memory test targeting the RAM array 10. The test control circuit 11 sends a request signal (hereinafter referred to as
(referred to as test request signal) TR.

Similarly, a function signal (hereinafter referred to as a test function signal) TF for specifying the type of memory access (read/write) and a select signal SEL for controlling selectors 20 to 22, which will be described later, are generated. There is.

Reference numeral 12 indicates R in response to a request signal R that requests memory access in the normal mode given from the arithmetic control unit or a test request signal TR from the test control circuit 11.
a RAM control circuit that controls access to the AM array 10;
Reference numeral 13 denotes an address switching circuit for switching addresses for the RAM array 10 (for example, switching between row addresses and column addresses).

14 is a check bit generator that generates a check bit for error detection/correction (ECC) based on the data (write data) to be written to the RAM array IO and outputs it to the RAM array 10; 15 is a read data error This is a detection/correction circuit. This error detection/correction circuit 15 is
Checks the read data (read data) from the M array IO, and when a single bit error is detected, corrects the data and sends a single bit error notification signal SB.
When a multi-bit error is detected, a multi-bit error notification signal MBE is output.

16 is a test address generator with a built-in counter that generates an address (test address signal) TA for the RAM array IO in the test mode under the control of the test control circuit 11; 17 is also a data (test data signal) T
This is a test data generator that generates D. Reference numeral 20 indicates a RAM control circuit 12 which selects either a function signal F for specifying the type of memory access in the normal mode given from the arithmetic control unit or a test function signal TF from the test control circuit 11 in response to a select signal SEL. A selector 21 selects and outputs an address signal A for normal mode (to the RAM array 10) given from the arithmetic control unit and a test address generator 16.
This selector selects and outputs one of the test address signals TA from the address switching circuit 13 according to the select signal SEL.

22 is a data signal D for normal mode from the arithmetic and control unit.
(write data) and the test data signal TD from the test data generator 17 to the RAM array IO according to the select signal SEL; In this case, the address at that time (error address), single-bit error notification signal SBE, and multi-bit error notification signal MBE are retained, and the status signal ST
This is a status register for notifying the outside of the system.

Next, we will explain the operation of the configuration shown in Figure 1: (a) in normal mode when the main storage is accessed from the arithmetic control unit in the computer system, and (b) in response to requests from the arithmetic control unit or other control units. The following describes the test mode in which the main storage device is tested. It is assumed that all the signals shown in FIG. 1 are active (true) at a high level.

(a) Operation in normal mode In normal mode, main memory access is performed as described below in response to a request from the arithmetic and control unit. First, in the case of write access, the arithmetic and control unit sends a request signal R requesting main memory access to the main memory device shown in FIG. 1 and a function signal F1 specifying write access.
Further, an address signal A and a write data signal D (write data) to the RAM array 10 are applied. On the other hand, in the case of a read access, a request signal R, a function signal F specifying read access, and an address signal A are applied to the main memory device from the arithmetic and control unit.

A function signal F given from the arithmetic control unit is supplied to one input (“0” inputs) of the selector 20. The other input (“1” input) of the selector 20 is supplied with the test function signal TF from the test control circuit. The selector 20 is controlled by a select signal SEL output from the test control circuit 11. This select signal SEL is "0" (low level) in the normal mode, and in this case, the function signal F from the arithmetic and control unit is selected. Further, the address signal A given from the arithmetic control unit is supplied to one input (“0” input) of the selector 21. A test address signal TA generated by a test address generator 1G is supplied to the other input of the selector 21 (the "1" side manual input). Furthermore, in the case of a write address, the data signal given from the arithmetic control unit is input to one input of the selector 22 (“0”
input). The other input of the selector 22 (“
1'' side input) is supplied with a test data signal TD generated by a test data generator 17.Selector 2
1.22 is the select signal SE from the test control circuit 11
In the case of 0° as in this example, the address signal A from the arithmetic control unit.

The data signal is selected. The address signal (here address signal A) selected by the selector 21 is supplied to the address switching circuit 13 and the status register 23. Further, the data signal selected by the selector 22 (data signal D here) is supplied to the RAM array IO and the check bit generator 14.

Address switching circuit 13 receives the address signal (address signal A) selected by selector 21, switches the address, and outputs it to RAM array IO. on the other hand,'
A request signal R given from the /fA'R control device is supplied to the RAM control circuit 12.

This RAM control circuit 12 receives a function signal F (from the arithmetic control unit) selected by the selector 20.
will also be supplied. RAM control circuit 12 in normal mode
outputs a group of RAM control signals for read access or write access to the RAM array 10 based on the request signal R and function signal F (from the arithmetic control unit). As a result, the address of the RAM array 10 specified by the address signal A (from the arithmetic control unit) selected by the selector 21 is read accessed or written accessed.

Now, during write access in the normal mode, the check bit generator 14 generates a corresponding check bit based on the data signal from the arithmetic control unit selected by the selector 22. This check bit is supplied to the RAM array 10 and written into the RAM array 10 together with the data signal D (write data).

On the other hand, during normal mode read access, a data signal (read data) specified by address signal A and the corresponding check bit are read from RAM array 10. Read data and check bits from the RAM array 10 are supplied to a read data error detection/correction circuit 15. The error detection/correction (ECC) circuit 15 checks the read data based on the read data and check bit from the error detection/correction circuit 15, and when a single bit error (1 and write error) is detected, Corrects and outputs the corresponding pit in the read data, and also outputs an active single-bit error notification signal SBE, and when a multi-bit error (an error of 2 or more bits) is detected, an active multi-bit error notification signal MB is output.
Outputs E. Furthermore, if there is no error, the error detection/correction circuit 15 outputs the read data from the RAM array 10 as is. This error detection/correction circuit 15
The principle of error detection and correction of standard data is well known and will not be explained here. The read data output from the error detection/correction circuit 15 is output from the main memory device as a data signal.

When the active single-bit error notification signal SBE or multi-bit error notification signal MBE is output from the error detection/correction circuit 15, the address signal (error address) at that time becomes the single-bit error notification signal S.
It is held in the status register 23 together with BE and multi-bit error notification signal MBE (state). The arithmetic and control unit can check the error status by reading the contents of the status register 23 of the main storage device as a status signal ST.

(b) Operation in test mode Next, we will explain the operation in test mode.When you want to test the main memory device (RAM array 10 within) shown in FIG. ,
An active test signal T is applied to the main memory. This test signal T is supplied to the test control circuit 11. When the test control circuit 11 receives the active test signal T, it sets the test mode and switches the select signal SEL from "0", which is the state in the normal mode, to "1" (high level), which is the state in the test mode. In this state, the test control circuit 11 receives a request signal R from the arithmetic control unit in order to access the RAM array 10.
A test request signal TR and a test function signal TF similar to the function signal F are generated. The test control circuit 11 also controls the test address generator 16 to generate the test address signal TA, and when the function signal TF specifies write access, the test control circuit 11 controls the test data generator 17 to generate the test address signal TA. A signal TD (write data for test) is generated.

The test control circuit 11 receives the above test request signal T.
R and the output of the test function signal TF, the test address generator 16 and the test data generator 17
This control is repeated at regular intervals such that write access to RAM array IO is performed in order from address 0 to the final address, and then read access to RAM array IO is performed in order from address 0 to final address. The test data generator 17 may always generate the same test data signal TD, a test data signal TD with a random value, or a test data signal TD generated by the test address generator 16. The same value as the address signal TA may be generated by a counter or the like.

Now, in the test mode, the select signal SEL is "1°
(high level), the test function signal TF output from the test control circuit 11
is selected by the selector 20. This test function signal TF is supplied to the RAM control circuit 12 together with the test request signal TR from the test control circuit 11.

The RAM control circuit 12 receives this test request signal TR.
and the function signal TF, outputs a group of RAM control signals for accessing the RAM array 10 in the same manner as when the request signal R and the function signal F from the arithmetic control unit are supplied. Control write or read access to. In the test mode, the test address signal TA generated by the test address generator 16 is selected by the selector 21, and in the case of write access, the test data signal TD generated by the test data generator 17 is selected by the selector 21. 22.

The test address signal TA and test data signal TD selected by the selectors 21 and 22 are the same as when the address signal A and data signal from the arithmetic control unit are selected in the normal mode, as described below. be treated.

First, in the case of write access in the test mode, the check bit generator 14 generates the test data signal T.
A check bit of D (test write data) is generated. This check bit is the test data signal TD.
(Test write data) is the test address signal TA
When data is written to the address of RAM array 10 specified by
written to. This write access is
This is performed in sequence from address O of O to the final address at a constant cycle.

When the series of write accesses described above is completed, the test control circuit 11 switches the test function signal TF from the write access designation state to the read access designation state. Further, the test control circuit 11 causes the test address generator 1B to sequentially generate test address signals TA from address O to the final address, as in the case of write access in the test mode. In read access in the test mode, the data signal (read data) specified by the test address signal TA and the corresponding check bit are read from the RAM array IO and subjected to an ECC check by the error detection/correction circuit 15. and,
When an error (single-bit error or multi-bit error) is detected, the address signal (error address) at that time is the single-bit error notification signal SBE, similar to when an error is detected during read access in normal mode. and multi-bit error notification signal MBE
It is also held in the status register 23. The arithmetic control unit can check the error status of the RAM array 10 by reading the contents of the status register 23 of the main storage device as a status signal ST.

The above is a RAM array 10 with one storage section of the main storage device.
(1 memory board), but the present invention is applicable to multiple RA
The present invention can also be applied to a memory test of a main memory device whose storage section is constituted by the M array 10 (a plurality of memory boards). In this case, each RAM array 10 (each memory board) is provided with a check bit generator 14, an error detection/correction circuit 15, and a status register 23, but other circuits, such as a test control circuit 11
, RAM control circuit 12, address switching circuit 13, test address generator 16, test data generator 17, and selectors 21 to 23 can be shared, and memory tests of multiple RAM arrays 10 (memory boards) can be performed by one RAM.
This can be performed in the same time as the memory test of the M array 10 (memory board). Note that in the case of the main memory device shown in FIG. 1, the address signal A from the arithmetic and control unit in the normal mode matches the main memory address; In this case, the lower part of the main memory address is used for the address signal A, and the remaining upper part is used for one of the RAM arrays 10.
It will be used as a signal to specify one.

In the above embodiment, a case has been described in which the status register 23 is used to hold status information when an error is detected by the error detection/correction circuit 15. It is also possible to use a ring buffer (circular buffer) or a register file. In this case, there is no risk that the status information that has already been collected will be rewritten by the status information that is collected subsequently, so the RA
This is convenient for grasping the error status of the entire M array 10. Furthermore, when using the status register 23,
It is also possible to grasp the error status of the entire RAM array IO by interrupting the 't1 arithmetic control device every time an error is detected, and causing the arithmetic control device to read the contents of the status register 23 each time. Further, in the above embodiment, a case was described in which the memory test was performed on a main memory device, but the present invention is applicable to general memory tests on memory devices included in information processing equipment.

[Effects of the Invention] As detailed above, according to the present invention, a memory device such as a main memory device is provided with a circuit that generates a test address and test write data in response to an external test request. In addition, a selector is provided to switch between this address and data and the address and data given from an external usage device to access the RAM array that constitutes a part of the memory of the storage device in a normal state.
Since the memory test of the RAM array is performed using the check bit generator and error detection/correction circuit inherent in the M array, the test program can be simplified and the memory device can be tested easily. Furthermore, since the RAM array can be tested inside the storage device, the test time can be shortened compared to the conventional method in which the memory test is performed by reading/writing from the outside. Furthermore, even if there are multiple memory boards, the time required to test a storage device is the same as the time spent on one board, which significantly reduces test time compared to conventional methods, especially when the storage device has a large capacity. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a main memory device to which the memory test method of the present invention is applied. JO...RAM array, 11...Test control circuit,
12... RAM control circuit, 13... Address switching circuit, 14... Check bit generator, 15... Read data error detection/correction circuit, 16... Test address generator, 17... Test data generator, 20-2
2...Selector, 2-3...Status register.

Claims (1)

[Scope of Claims] In a memory test method for a storage device whose storage unit is constituted by a RAM array accessed from an external usage device, a test signal for requesting a memory test is applied from the outside to enable normal mode. a test control circuit that controls a memory test by switching to a test mode from the start; a test address generator that generates a test address for testing the RAM array under the control of the test control circuit; and a test address generator that controls the test control circuit. a test data generator that generates test write data when testing the RAM array; and a test data generator that generates test write data when testing the RAM array. A RAM array control circuit that controls reading/writing to the RAM array, and a RAM array control circuit that uses the address given from the above-mentioned device in normal mode and the test address generated by the above-mentioned test address generator in test mode to access the above-mentioned RAM array. A first selector that selects an address, and in the case of write access, write data provided from the usage device in the normal mode, and test write data generated by the test data generator in the test mode, to the RAM array. a second selector that selects data to be written to the RAM array; and a check bit that generates a check bit for error detection and correction based on the data selected by the second selector and outputs it to the RAM array. and a generator, and in the case of a read access, performs error detection and correction based on the data read from the RAM array according to the designation of the address selected by the first selector and the check bit of the data. It is equipped with an error detection/correction circuit, and a status holding means for holding error status information including the address at that time when an error is detected by the error detection/correction circuit, and is configured to respond to an external test signal. 1. A memory test method characterized in that a memory test of a RAM array constituting a storage section of a storage device is performed inside the storage device.