JPH0449450A - Memory test system - Google Patents

Abstract

PURPOSE:To shorten a testing time by providing the memory test system with a means for storing error status information including an address used at the time of a reading access in a test mode in accordance with the discrepancy detection of a comparator. CONSTITUTION:When a test signal is applied from the external to a storage device, an external using device is switched from a normal mode for accessing a storage device to a test mode for executing a memory test of a RAM array 10 in the storage device. Data read out from the RAM array 10 are compared with data selected and outputted from a selector 22 by the comparator 15. At the time of a memory error in which both the data are not equal and coincidence is detected, status information including the address used for the test mode is stored in the status storing means 23. Thereby, the using device can grasp the error status of the RAM array 10 in the storage device only by reading out the contents of the means 23. Thus, the testing time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a memory test method for testing a storage device included in an information processing device.

(Prior Art) Generally, a computer system includes an arithmetic and control unit that serves as the control center of the system, and a main memory that is used to store various programs and data.

This main memory device is composed of a semiconductor memory element (RAM), and its capacity (main memory capacity N) is increasing year by year due to advances in semiconductor technology and high-density packaging technology.

Conventionally, testing of a main memory device (memory test) has been carried out by using a test program based on a combination of instructions, and having an arithmetic control unit, which forms the core of a computer system, execute this test program.

(Problems to be Solved by the Invention) As described above, in the conventional memory test method, the arithmetic and control unit reads/writes data in the main memory according to a test program. For this reason,
The disadvantage is that the time required for testing (test time) also increases in proportion to the installed capacity of the main memory, which is a particular problem when testing a large capacity main memory.

This invention was made in view of the above circumstances, and its purpose is to provide a memory test method that can easily perform memory tests on storage devices, such as main storage devices, and that can shorten the time required for memory tests (test time). Our goal is to provide the following.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a system in which a test signal for requesting a memory test of a storage device such as a main storage device whose storage section is constituted by a RAM array is sent to the device from outside. The test control circuit switches from the normal mode to the test mode to control the memory test, and the test address for testing the RAM array can be accessed for write access and read access for all addresses in the RAM array. A test address generator that separately generates in a fixed order,
RAM that controls reading/writing to the RAM array
An array control circuit, a first selector that switches the address given by the usage device and a test address generated by the test address generator as the address of the RAM array, and a first selector that switches the address of the RAM array between the address given by the usage device and the write data given from the usage device. In test mode, a test address generated by a test address generator (or fixed test data generated by a test data generator) is selected, and in write access, a second a selector, a comparison circuit that compares the data read from the RAM array according to the designation of the address selected by the first selector and the data selected by the second selector to detect a match/mismatch; and a test mode. and a status holding means for holding error status information including the address at that time in response to mismatch detection of the comparison circuit during read access in the storage device.
This is characterized in that it performs a memory test for M arrays.

(Operation) According to the present invention, when a test signal is applied to a storage device such as a main storage device from the outside, the RA is changed from a normal mode in which an external usage device accesses the storage device to an RA inside the storage device.
The test mode is switched to perform a memory test of the M array. In this test mode, the test address generator is controlled by the test control circuit.
First, test write addresses used in write access are generated, for example from the first address to the last address of the RAM array, and then test read addresses used in read access are generated from the first address to the last address of the RAM array. .

Now, in the test mote, by the selection operation of the first selector and furthermore the second selector, instead of the address and data (write data) given from the external usage device in the normal mode, the test address generator generates the address and data (write data). The test write data is used for the test address and history. This test write data uses a test address (or a fixed test pattern generated by a test data generator configured using a dip switch or the like). Then, when write access in test mode is performed from the first address to the last address of the RAM array based on the selected address and test write data, the write access is switched to read access under the control of the test control circuit. , RAM
Data specified by the test address is read from the array. This read data from the RAM array is compared with data selectively output from the second selector (same as test write data used in write access for the same test address) by a comparison circuit.

Here, in the event of a memory error in which both data are not equal and a mismatch is detected, status information including the test address (error address) at that time is held in the status holding means. Therefore, the utilization device can grasp the error status of the RAM array of the storage device simply by reading the contents of this status holding means.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a main storage device in a computer system to which the present invention is applied. In the figure, IO constitutes a storage section of the main memory device and is a RAM array to be subjected to a memory test, and 11 indicates a test mode in response to a test signal T given from an arithmetic control unit or other control unit (not shown). This is a test control circuit for setting and controlling a patented memory test featuring the RAM array 1o. The test control circuit 11 generates a request signal (hereinafter referred to as a test request signal) TR for requesting memory access to (the RAM array 10 constituting) the main storage device in the test mode.

Similarly, a function signal (hereinafter referred to as test function signal) TF for specifying the type of memory access (read/write), a select signal 5ELI (1 bit) that controls selectors 20, 21 and 22, which will be described later, and 5EL2 (2 bits)
etc. is generated.

Reference numeral 12 indicates R in response to a request signal R that requests memory access in the normal mode given from the arithmetic control unit or a test request signal TR from the test control circuit 11.
a RAM control circuit that controls access to the AM array 10;
Reference numeral 13 denotes an address switching circuit for switching addresses for the RAM array IO (for example, switching between row addresses and column addresses).

Reference numeral 15 denotes a comparison circuit for checking the read data (read data) from the RAM array IO by comparing the same data with selected output data from the selector 22, which will be described later, and detecting a match/mismatch. is a test address generator with a built-in counter that generates an address (test address signal) TA for the RAM array IO in the test mode under the control of the test control circuit 11.

This test address signal TA can also be used as test data (test data signal) TDI, which will be described later.

17 and 18 are fixed test data (test data signals) TD2. This is a test data generator for generating TD3. Test data generator 17.1
8 is configured using a dip switch, for example,
Test data signal TD according to the setting state of the switch
2. It is designed to generate TD3. Here, the test data generators 17.18 are all 5 in hexadecimal representation.
(#5-5), all A (#A-A) test data signal TD2. It is set to generate TD3.

Note that the test data signal TD2. If it is okay for TD3 to remain constant at all times, it can be generated simply by combining VCC (power supply voltage) and GND (ground) without using special equipment such as dip switches, and the circuit configuration is significantly simplified. Simplified.

20 is a function signal F for specifying the type of memory access in the normal mode given from the arithmetic control unit.
and a selector 21 for selectively outputting one of the test function signals TF from the test control circuit 11 to the RAM control circuit 12 in accordance with the select signal 5ELI.
selects either one of the normal mode address signal A given from the arithmetic control unit (to the RAM array IO) and the test address signal TA from the test address generator 16 to the address switching circuit 13 in accordance with the select signal 5EL1. This is the selector to output. 22 is a data signal D (write data) for normal mode from the arithmetic control unit, a test address signal TA (i.e., test data signal TD1) from the test address generator 1G, and a data signal from the test data generators 17 and 18. Test data signal TD2. Select signal 5EL2 for one of TD3
a selector 2 for selectively outputting to the RAM array 10 according to the
3 holds the address (error address) and the output signal (error notification signal) of the comparison circuit 15 when a mismatch is detected in the comparison circuit 15 during read access in the test mode, and notifies it to the outside as a status signal ST. This is a status register for

Next, we will explain the operation of the configuration shown in Figure 1: (a) in normal mode when the main storage is accessed from the arithmetic control unit in the computer system, and (b) in response to requests from the arithmetic control unit or other control devices. The test mode, in which the main memory is tested, will be explained in order. In addition, the first
It is assumed that all the signals shown in the figure are active (true) at a high level.

(a) Operation in normal mode In normal mode, main memory access is performed as described below in response to a request from the arithmetic and control unit. First, in the case of write access, a request signal R requesting main memory access, a function signal F1 specifying write access, and an address to the RAM array IO are sent from the arithmetic and control unit 4 to the main memory shown in FIG. A signal A and a write data signal D (write data) are provided. On the other hand, in the case of a read access, a request signal R, a function signal F specifying read access, and an address signal A are applied to the main memory device from the arithmetic and control unit.

The function number F obtained from the arithmetic and control unit is supplied to one input (“0” sub-input) of the selector 20. The other input (“1” sub-input) of the selector 20 receives the test function signal T from the test control circuit 11.
F is supplied. The selector 20 is controlled by a select signal 5ELI output from the test control circuit 11.

This select signal SEL1 is normally “0” in the mote.
” (low level), and in this case, the function signal F from the arithmetic and control unit is selected.

Further, the address signal A given from the arithmetic control unit is supplied to one input (“O” sub-input) of the selector 21.

The other input (“1” sub-input) of the selector 21 is supplied with a test address signal TA generated by a test address generator I6.

The selector 21 is controlled by the select signal 5ELI from the test control circuit 11, and when it is "0" as in this example, the address signal A from the arithmetic control unit is selected. The address signal (here address signal A) selected by the selector 21 is supplied to the address switching circuit 13 and the status register 23.

Furthermore, in the case of write access, a data signal is given from the control device. This data signal is supplied to the 0th input (“0” sub-input) of the selector 22. Further, the test address signal TA generated by the test address generator 1B is supplied to the first input (“1” sub-input) of the selector 22 as the test data signal TDI,
Second. The third input (“2” side, “3” sub-input) is the test data signal TD2. generated by the test data generator 17.18. TD3 is supplied. The selector 22 receives a 2-bit select signal 5EL from the test control circuit 11.
2. This select signal 5EL2 is usually "0" among "0" to "3" in the mode, and in this case, the data signal from the arithmetic and control unit is selected. The data signal selected by the selector 22 (
Here, the pig signal D) is supplied to the RAM array 10 and the comparator circuit 15.

The address switching circuit 13 receives the address signal (address signal A) selected by the selector 21, switches the address, and outputs it to the RAM array 10. On the other hand, a request signal R given from the arithmetic and control unit is supplied to the RAM control circuit 12.

This RAM control circuit 12 receives a function signal F (from the arithmetic control unit) selected by the selector 20.
will also be supplied. RAM control circuit 12 in normal mode
outputs a group of RAM control signals for read access or physical access to the RAM array IO based on the request signal R and function signal F (from the arithmetic control unit).

As a result, if write access is specified by function signal F in normal mode,
RAM array 10 is write accessed and selector 21
The data signal (from the arithmetic control unit) selected by the selector 22 is written to the address indicated by the address signal A (from the arithmetic control unit) selected by the selector 22 .

On the other hand, if read access is specified in the normal mode, the RAM array 10 is read accessed, and the data at the address indicated by the address signal A (from the arithmetic control unit) selected by the selector 21 is read out. . The read data from the RAM array IO is output from the main memory device as a data signal.

(b) Operation in test mode Next, the operation in test mode will be explained.

When it is desired to test the main memory device (RAM array 10 within) shown in FIG.
An active test signal T is applied to the main memory. This test signal T is supplied to the test control circuit 11. When the test control circuit 11 receives the active test signal T, it sets the test mode and selects the select signal 5ELI.
is switched from "O", which is the state in normal mode, to "1" (high level), which is the state in test mode. In this state, the test control circuit 11 generates a test request signal TR and a test function signal TF similar to the request signal R and function signal F from the arithmetic control unit in order to access the RAM array 10. The test control circuit 11 also controls the test address generator 16 to generate a test address signal TA. The test control circuit 11 outputs the above-described test request signal TR and test function signal TF, and controls the test address generator 16 such that write access to the RAM array IO is performed in order from address 0 to the final address, for example. Thereafter, read access to the RAM array 10 is repeated at regular intervals so that read access is performed sequentially from address 0 to the final address.

Now, in the test mode, the select signal 5ELI is switched to "1" (high level) as described above. In this case, the test function signal TF output from the test control circuit 11 is selected by the selector 20. This test function signal TF is sent to the RAM together with the test request signal TR from the test control circuit 11.
The signal is supplied to the control circuit 12. Based on the test request signal TR and function signal TF, the RAM control circuit 12 performs a process for accessing the RAM array 10 in the same manner as when the request signal R and function signal F from the arithmetic control unit are supplied. It outputs a group of RAM control signals and controls write access or read access to the RAM array 10.

Further, in the test mode, the test address signal TA generated by the test address generator 16 is selected by the selector 21 in response to the select signal 5ELI of logic "1#". The signal 5EL2 is switched from "O" to any one of "1" to "3".This select signal 5EL
The state of 2 remains unchanged during one test mode. When the select signal 5EL2 is one of "1' to "3", the test data signal TDI which is the test address signal TA generated by the test address generator 16
and the test data signal TI generated by the test data generators 17 and 18)2. One of TD3 is selected. The test address signal TA selected by the selector 21 is handled in the same way as when the address signal A from the arithmetic control unit is selected in the normal mode, as described below. In addition, the test data signal TDi (i is one of 1 to 3) selected by the selector 22 is different from the case where the data signal from the arithmetic control unit is selected in the normal mode, as described below, at the time of write access. be treated similarly. However, during read access,
Test data signal T selected by selector 22
Di is treated as reference data for checking memory errors in the RAM array 10.

First, in the case of write access in the test mode, the test data signal TD selected by the selector 22
i is written to the address of the RAM array IO specified by the test address signal TA selected by the selector 21. This write access is performed sequentially at a constant cycle from address O to the final address of RAM array IO. As a result, the selector 22 selects the test data signal TD.
In the test mode in which I (that is, test address signal TA) is selected, if RAM array IO is normal, each address C of RAM array 10 is written with the same value as that address. Similarly, in the test mode in which the test data signal TD2 or TD3 is selected by the selector 22, data of all 5 or all A is written to each address of the RAM array 10.

When the series of write accesses in the test mode described above is completed, the test control circuit 12 switches the test function signal TF from the write access designation state to the read access designation state.

In addition, the test control circuit 11 sends the test address signal TA from address 0 to the final address to the test address generator 16, as in the case of write access in the test mode.
are generated in order. As a result, in the test mode, read access to the RAM array 10 is performed in order from address 0 to the final address, and each time a data signal (read data) at the address specified by the test address signal TA is read from the RAM array 10. be done.

Now, select signal 5EL2 from test control circuit 11
The period of a series of read accesses in the test mode is also maintained in the same state as the period of write accesses described above. Therefore, if the test data signal TDI (-test address signal TA) is selected by the selector 22 (as write data) during the write access period in the test mode, the same test will be performed during the next read access period. data signal TDI (-test address signal TA) is selected. Similarly, during the write access period in the test code, the test data signal TD2
(all 5), TD3 (all A) are selected by the selector 22 (as write data), the same test data signals TD2 (all 5), TD3 (all A) are used during the next read access period. ) is selected.

Test data signal TD selected by selector 22
i (i is any one of 1 to 3) is supplied to one input of the comparison circuit 15. The other input of the comparator circuit 15 has RA
Test address signal TA read from M array 10
Data at the address specified by is supplied. Comparison circuit 1
5 compares both of the above data. Select signal 5EL2
The status is “1” to “3” during one test mode period.
In this embodiment, the data at the address specified by the test address signal TA read from the RAM array 10 is the test data selected by the selector 22 if the data is correct. Signal TD
It should match i. Therefore, it is possible to notify whether there is a memory error or not by detecting a match/mismatch through comparison by the comparator circuit 5. Note that the comparator circuit 15 is controlled to operate effectively only during read access in the test mode.

The output signal of the comparison circuit 15 is supplied to the status register 23 as an error notification signal. The test address signal TA selected by the selector 21 is also supplied to the status register 23 .

This test address signal TA is held in the status register 23 together with the output signal (error notification signal) of the comparison circuit 15 (if a mismatch is detected by the comparison circuit 15 during read access in the test mode). The arithmetic control unit can check the error status of the RAM array 10 by reading the contents of the status register 23 of the main storage device as a status signal ST.

The above is a RAM array 10 with one storage section of the main storage device.
(one memory board), the present invention is also applicable to multiple RA
It can also be applied to a memory test of a main memory device whose storage section is constituted by M array l0 (I number of memory boards). In this case, each RAM array 10 (each memory board) is provided with a comparison circuit 15 and a status register 23, or is provided with other circuits, such as a test control circuit 1.
1, RAM control circuit 12, address switching circuit 13, test address generator 1B, test data generator 17.18
and the selectors 20 to 22 can be shared, and can be used by multiple R
It is possible to perform a memory test of the AM array 10 (memory board) in the same time as a memory test of one RAM array 10 (memory board). Note that in the case of the main memory device shown in FIG. 1, the address signal A from the arithmetic and control unit in the normal mode matches the main memory address; In this case, the lower part of the main memory address is used for the address signal A, and the remaining upper part is used for the RAM array l.
It will be used as a signal to designate one of O.

In the above embodiment, in addition to using the test address generator 16 as a test data generator, dedicated test data generators 17 and 18 are provided, and various test data can be used. Test data generator L7.1B is not absolutely necessary. In this case, the circuit can be further simplified. However, the test data signal TD2. generated by the test data generator 17.18. If you don't mind that TD3 is always fixed, simply set V
It can be generated simply by combining CC (power supply voltage) and GND (ground), and a special test data generator is not required, and the circuit can be simplified.

Further, in the above embodiment, the comparison circuit 15 detects a mismatch (
Although we have described the case where the status register 23 is used to hold status information when an error) is detected, it is also possible to use a ring buffer or register file that can store multiple pieces of status information. It is also possible to use In this case, there is no risk that the status information that has already been collected will be rewritten by the status information that is collected subsequently, so the RA
This is convenient for grasping the error status of the entire M array IO. Furthermore, when using the status register 23,
It is also possible to grasp the error status of the entire RAM array IO by interrupting the arithmetic and control unit every time an error is detected, and causing the arithmetic and control unit to read the contents of the status register 23 each time.

Further, in the above embodiment, a case was described in which the memory test was performed on a main memory device, but the present invention is applicable to general memory tests on memory devices included in information processing equipment.

[Effects of the Invention] As detailed above, according to the present invention, there is provided a circuit that generates a test address, which is also used for test data, in a storage device such as a main memory device in response to an external test request. and a selector for switching between the test address and test data and the address and data given from an external device for accessing the RAM array constituting the storage section of the storage device in the normal state. In addition to controlling addresses and data in the same way during write access and read access,
The memory test of the RAM array is performed by comparing the data read from the RAM array by read access in the test mode with the data switched and output by the selector using a comparison circuit.
The effects listed below can be obtained.

■ The test program can be simplified and the storage device can be easily tested.

■ RA within the storage device in response to external test requests
Since the M array can be tested automatically, the test time can be reduced compared to the conventional method in which memory tests are performed sequentially by reading/writing from the outside.

■ The time required to test a storage device is the same as the time spent on one board, even if there are multiple memory boards.
Especially when the storage device has a large capacity, the test time can be significantly reduced compared to the conventional method.

■ Can be achieved with a small number of test circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a main memory device to which the memory test method of the present invention is applied. 10... RAM array, 11... test control circuit,
I2...RAM control circuit, I3...Address switching circuit, 15...Comparison circuit, 16...Test address generator, 17, 1'8...Test data generator, 20~
22...Selector, 23...Status register. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) In a memory test method for a storage device whose storage unit is made up of a RAM array that is accessed from an external device, a test signal for requesting a memory test is applied from the outside to switch from normal mode to test mode. A test control circuit that controls the memory test by switching to the memory test; and a test control circuit that controls the memory test by controlling the test address for testing the RAM array for each write access and read access for all addresses of the RAM array. A test address generator that separately generates in a fixed order, and a RAM array control that controls read/write to the RAM array in response to an access request from the above-mentioned device in normal mode, and in response to an access request from the test control circuit in test mode. a first selector that selects an address given from the utilization device in a normal mode and a test address generated by the test address generator in a test mode as an address for accessing the RAM array; In the normal mode, the write data given from the utilization device is selected, in the test mode, the test address generated by the test address generator is selected, and in the write access, the second selector is used to select the write data of the RAM array. and a comparison circuit that compares the data read from the RAM array according to the designation of the address selected by the first selector and the data selected by the second selector to detect coincidence/mismatch. a status holding means for holding error status information including the address at that time in response to a mismatch detected by the comparison circuit during read access in the test mode; A memory test method characterized in that a memory test is performed on a RAM array constituting a storage section of the device. (2) In a memory test method for a storage device whose storage unit is made up of a RAM array that is accessed from an external usage device, the test mode changes from normal mode to test mode by applying a test signal to request a memory test from the outside. A test control circuit that controls the memory test by switching to the memory test; and a test control circuit that controls the memory test by controlling the test address for testing the RAM array for each write access and read access for all addresses of the RAM array. A test address generator that separately generates in a fixed order, and a RAM array control that controls read/write to the RAM array in response to an access request from the above-mentioned device in normal mode, and in response to an access request from the test control circuit in test mode. a first selector that selects an address given from the utilization device in a normal mode and a test address generated by the test address generator in a test mode as an address for accessing the RAM array; At least one test data generator for generating fixed test data; in normal mode, the write data given from the above-mentioned utilization device; in test mode, the test address generated by the above-mentioned test address generator and the above-mentioned test data generation; select one of the test data generated by the device,
a second selector used for selecting write data in the RAM array during write access; and data read out from the RAM array in accordance with designation of the address selected by the first selector and the second selector. A comparison circuit that compares the data selected by and detects a match/mismatch, and a status hold that maintains error status information including the address at the time of read access in test mode, depending on the mismatch detected by the comparison circuit. 1. A memory test method, comprising: means for performing a memory test of a RAM array constituting a storage section of the storage device within the storage device in response to a test signal from the outside.