JPH04251355A - Memory test system - Google Patents

Abstract

PURPOSE:To easily perform a memory test on a storage device having a storing section of a RAM array constitution composed of plural banks in the storage device itself in a short time. CONSTITUTION:When a test mode is set in accordance with a test signal T from the outside, a bank switching circuit 23 selects all banks #0-#3 irrespective of address signals. The writing operations of fixed data from a test data generator 27 are successively performed at all addresses by simultaneously making access to the same address of the banks #0-#3 by controlling a RAM control circuit 22 and test address generator 26 by means of a test control circuit 21 under such state. Then memory error detection is performed by successively carrying out such operations that simultaneously make read access to the same address of the banks #0-#3 at all addresses under the control of the circuit 21 and comparing the read-out data with the test data form a test data generator 27 at a comparator circuit 25.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test method for testing a storage device having a plurality of banks.

0002

2. Description of the Related Art Generally, a computer system includes an arithmetic and control unit that serves as the control center of the system, and a main memory that stores various programs and data. This main memory device is composed of a semiconductor memory element (RAM), and its capacity (main memory capacity) is increasing year by year due to advances in semiconductor technology and high-density packaging technology.

Conventionally, main memory testing (memory testing) uses a test program based on a combination of instructions.
This was done by having the arithmetic and control unit, which forms the core of the computer system, execute this test program.

0004

As described above, in the conventional memory test method, the arithmetic and control unit reads/writes data in the main memory according to a test program. Therefore, the time required for testing (
The disadvantage is that the test time (test time) also increases in proportion to the installed capacity of the main storage device, which is a particular problem when testing a large-capacity main storage device with a plurality of banks.

The present invention has been made in view of the above circumstances, and its purpose is to provide a memory test method that allows a memory test of a storage device having a plurality of banks to be easily performed inside the storage device, and further reduces the time required for the memory test. It is about providing.

[0006]

[Means for Solving the Problems] The present invention provides a method for switching from a normal mode to a test mode by externally applying a test signal to a storage device having a storage section having a RAM array configuration consisting of a plurality of memory banks. A test control circuit that controls a memory test, a test address generator that generates test addresses in a fixed order for each write access and read access for all addresses in the bank, and fixed test data set in advance. or a test data generator that generates test data corresponding to each address of the bank in a fixed order in synchronization with the operation of the test address generator, and a RAM array control circuit that controls read/write to the RAM array. , a bank switching circuit that controls bank switching and selects all banks in the test mode, and a first circuit that switches between the address given by the device to be used and the test address generated by the test address generator as the address of the RAM array. selector and the write data given from the device being used in the normal mode, and the test data generated by the test data generator (or the test address generated by the test address generator) in the test mode, in the RAM.
A second selector selects data to be written to the array, and data read from each bank according to the address selected by the first selector during read access in test mode and data selected by the second selector. a comparison circuit for detecting a match/mismatch by comparing the detected data, and a status holding means for holding error status information including an address at that time in response to the detection of a mismatch by the comparison circuit. Prepare,
The present invention is characterized in that a memory test of a RAM array is performed inside the storage device in response to a test signal from the outside.

[0007]

[Operation] According to the above configuration, when a test signal is applied to a storage device such as a main storage device from the outside, a memory test of the RAM array is performed inside the storage device from a normal mode in which an external user device accesses the storage device. Switches to test mode for performing. In this test mode, the test address generator is controlled by the test control circuit to first generate test write addresses (addresses within the bank) used in write accesses from the first address to the last address, and then Test read addresses (addresses within the bank) used in the test are generated from the first address to the last address. Under the control of the RAM array control circuit, write access to the RAM array is performed during the test write address generation period, and read access to the RAM array is performed during the test read address generation period.

Now, in the test mode, all banks are selected by the bank switching circuit. Furthermore, in the test mode, by the selection operation of the first selector, a test address generated by the test address generator is used in place of the address given from an external usage device in the normal mode. In addition, in the test mode (in the case of write access), the selection operation of the second selector causes the test data generated by the test data generator (
Fixed test data or test data determined by a test address generated by a test address generator is used. As this test data, it is also possible to use a test address from a test address generator, and in this case, the test data generator is not required.

As described above, during the first write access in the test mode, fixed test data (or test data determined by that address, or a test address with the same value as that address) is stored at the same address in each bank. The simultaneous writing operations are performed in order from the first address to the last address.

When write access to all addresses in each bank is completed, the test control circuit switches to read access. As a result, the operation of simultaneously reading data written in the previous write access period from the same address in each bank is performed sequentially from the first address to the last address. Each piece of data read simultaneously from the same address in each bank is compared by a comparison circuit with the data (same as the test data used in write access for the same test address) selectively output from the second selector. Ru. Here, when a memory error occurs in which a mismatch is detected by the comparison circuit, status information including the test address (error address) at that time is held in the status holding means. Therefore, the utilization device can grasp the error status of the RAM array of the storage device simply by reading the contents of this status holding means.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a main storage device in a computer system to which the present invention is applied.

In FIG. 1, reference numerals 10 to 13 are RAM arrays constituting the storage section of a main memory device consisting of a plurality of memory banks, and are mounted on one memory board. R.A.
M arrays 10 to 13 are memory banks #0 to #3, respectively.
Configure.

21 sets a test mode in accordance with a test signal T given from an external device (not shown) represented by an arithmetic and control unit, and
0 to #3) is a test control circuit for controlling a memory test. The test control circuit 21 receives a test mode signal TM for effectively operating a comparison circuit 25, which will be described later, and an R
A request signal (hereinafter referred to as a test request signal) TR for requesting memory access to the AM arrays 10 to 13) and a function signal (hereinafter referred to as a test function) for specifying the type of memory access (read/write) TF (referred to as a signal) is generated. The test control circuit 21 also includes a selector 3 which will be described later.
A select signal SEL for controlling banks 1 to 33 and a test bank signal TB for requesting the bank switching circuit 23 to select all banks (banks #0 to #3) are generated.

Reference numeral 22 indicates R for controlling access to the RAM arrays 10 to 13 in response to a request signal R requesting memory access in the normal mode applied from an external device or a test request signal TR from the test control circuit 21.
The AM control circuit 23 is a bank switching circuit for switching memory banks. The bank switching circuit 23 normally (in normal mode) selects (switches) the bank specified by the address signal (inner bank address) selectively output from the selector 32, and performs a test in which the test bank signal TB becomes active. mode, all banks (bank #0
to #3).

24 is an address switching circuit for switching addresses for the RAM arrays 10 to 13 (for example, switching row addresses and column addresses); 25 is a RAM array 10;
This is a comparison circuit that performs data comparison for memory error checking of 1 to 13. The comparison circuit 25 compares the RAM arrays 10 to 1 during the period when the test mode signal TM is active.
Each read data (read data) from 3 and selector 3
The selected output data from 3 are compared with each other to detect coincidence/mismatch.

26 is a test address generator with a built-in counter that generates an address (test address signal) TA for the RAM arrays 10 to 13 in the test mode under the control of the test control circuit 11; 27 is a test address generator that generates preset test data ( This is a test data generator 27 for generating a test data signal (TD) in a test mode. The test data generator 27 is configured using, for example, a dip switch, and generates a test data signal TD according to the setting state of the switch. Note that if the test data signal TD does not need to be fixed at all times, it can be generated simply by combining VCC (power supply voltage) and GND (ground) without using any special equipment such as a dip switch. By doing so, the circuit configuration can be simplified.

Reference numeral 31 selects either the function signal F for specifying the type of memory access in the normal mode given from an external device or the test function signal TF from the test control circuit 21 as a select signal SE.
This is a selector that selectively outputs to the RAM control circuit 22 in accordance with L. 32 is an address switching circuit 24 which selects either one of the normal mode address signal A (to the RAM arrays 10 to 13) given from an external device and the test address signal TA from the test address generator 16 in accordance with the select signal SEL. A selector 33 selectively outputs either the normal mode data signal D (write data) from an external device or the test data signal TD from the test data generator 27 to the RAM array 10 in accordance with the select signal SEL. 13 (and comparison circuit 25). 34 is an address (error address) and an output signal of the comparison circuit 25 (4-bit error notification signal) when a mismatch is detected in the comparison circuit 25 during read access in the test mode.
This is a status register for holding and notifying the outside as a status signal ST.

Next, we will explain the operation of the configuration shown in FIG. 1 in (a) a normal mode in which the main memory is accessed from an external device (main memory utilization device) represented by an arithmetic and control unit, and (b) in an external device. The explanation will be given separately for the test mode in which the main storage device is tested in response to a request from the main storage device. In addition, Figure 1
It is assumed that all the signals shown in are active (true) at high level.

(a) Operation in normal mode In normal mode, main memory access is performed as described below in response to a request from an external device such as an arithmetic control unit.

First, in the case of write access, an external device sends a request signal R requesting main memory access to the main memory device shown in FIG. Address signal A and write data signal D (write data) for (any one of) are given. On the other hand, in the case of read access, a request signal R, a function signal F specifying read access, and an address signal A are applied to the main memory device from an external device.

A function signal F given from an external device is supplied to the "0" side input of the selector 31. A test function signal TF from the test control circuit 21 is supplied to the “1” side input of the selector 31 . The selector 31 is controlled by a select signal SEL output from the test control circuit 21. This select signal SEL is "0" (low level) in the normal mode, and in this case, the function signal F from the external device is selected. Note that in the normal mode, the test bank signal TB and test mode signal TM from the test control circuit 21 are also “0”.
becomes.

Next, the address signal A given from the external device is supplied to the "0" side input of the selector 32. The test address generator 16 is connected to the “1” side input of the selector 32.
A test address signal TA generated by the test address signal TA is supplied. The selector 32 is controlled by the select signal SEL from the test control circuit 21, and when it is "0" (normal mode) as in this example, it selects the address signal A from the external device. The address signal selected by the selector 32 (here address signal A) is supplied to the status register 34. The bank address, which is the upper two bits of the address signal selected by the selector 32, is sent to the bank switching circuit 23, and the remaining address (RAM
(array address, in-bank address) are respectively supplied to the address switching circuit 24.

Since the test bank signal TB is "0" in the normal mode, the bank switching circuit 23 selects the selector 3.
Address signal selectively output from 2 (address signal A)
Bank switching is performed to select memory bank #i (i is any one of 0 to 3) specified by the bank address inside. Further, the address switching circuit 24 receives the RAM array address (address within the bank) in the address signal (address signal A) selectively output from the selector 32, switches the address, and outputs the address to the RAM arrays 10-13.

Next, in the case of write access, the data signal D applied from an external device is supplied to the "0" side input of the selector 33. A test data signal TD generated by a test data generator 27 is supplied to the “1” side input of the selector 33 . Selector 33 is test control circuit 2
1, and when it is "0" (normal mode) as in this example, the data signal D from the external device is selected. The data signal (here, data signal D) selected by the selector 33 is R
It is supplied to AM arrays 10 - 13 and comparison circuit 25 .

Further, a request signal R given from an external device is supplied to the RAM control circuit 22. This RAM
The control circuit 22 has (
A function signal F (from an external device) is also supplied. In the normal mode, the RAM control circuit 22 receives a request signal R (from an external device) and a function signal F.
Based on the RAM arrays 10 to 13 (banks #0 to #3
) for read or write access
Outputs AM control signal group.

As a result, if write access is specified by function signal F in the normal mode, RAM arrays 10 to 13 (banks #0 to #
Among 3), the RAM array (bank) switched by the bank switching circuit 23 is write-accessed. Then, selector 3 in this RAM array (bank)
The RAM array address (address in the bank) indicated by the address signal A (from the external device) selected by the selector 33 (from the external device) is selected by the selector 33 (from the external device).
Data signal D is written.

On the other hand, if read access is specified in the normal mode, the RAM array (bank) being switched by the bank switching circuit 23 is read accessed. Then, data at the RAM array address (address in the bank) indicated by the address signal A selected by the selector 32 is read out from this RAM array (bank). This read data is the data signal D
is output from the main memory as

(b) Operation in test mode Next, the operation in test mode will be explained. When the external device desires to test the main memory device (RAM arrays 10 to 13 within) of FIG. 1, it supplies an active test signal T to the main memory device to instruct the main memory device to start the test. This test signal T is supplied to the test control circuit 21.

When the test control circuit 21 receives an active test signal T from an external device, it sets the test mode and changes the state of the select signal SEL to "0" in the normal mode.
” to “1” (high level). In this state, the test control circuit 21 receives a test request signal TR similar to the request signal R and function signal F from the external device in order to access the RAM arrays 10 to 13. The test control circuit 21 also controls the test address generator 26 to generate the test address signal TA.

The test control circuit 21 receives the above test request signal TR and test function signal TF.
The output of the RA and the control of the test address generator 26 are connected to the RA.
For example, write access to M arrays 10 to 13 is 0.
Read access is performed sequentially from the address to the final address, and then read access to the RAM arrays 10 to 13 is performed sequentially from address 0 to the final address, and is repeated at regular intervals.

The test control circuit 21 also sets the test bank signal TB supplied to the bank switching circuit 23 to a high level ("1") during the test mode. Thereby, the bank switching circuit 23 selects all banks #0 to #3 (RAM arrays 10 to 13) regardless of the content of the bank address in the address signal selectively outputted from the selector 32. Therefore, during the test mode, all banks #
The same locations of RAM arrays 0 to #3 (RAM arrays 10 to 13) are accessed at the same time.

Now, in the test mode, the select signal S
EL is switched to "1" (high level) as described above. In this case, the test function signal TF output from the test control circuit 21 is selected by the selector 31. This test function signal TF is supplied to the RAM control circuit 22 together with the test request signal TR from the test control circuit 21. RAM control circuit 2
2 performs RAM control for accessing the RAM arrays 10 to 13 based on the test request signal TR and function signal TF in the same manner as when the request signal R and function signal F from an external device are supplied. It outputs a group of signals and controls write access or read access to the RAM arrays 10 to 13.

In the test mode, the test address signal TA generated by the test address generator 26 is selected by the selector 32 in response to the select signal SEL of logic "1". Similarly, the test data signal TD generated by the test data generator 27 is selected by the selector 33.

The test address signal TA selected by the selector 32 is handled in the same way as when the address signal A from the external device is selected in the normal mode, as described below. Furthermore, the test data signal TD selected by the selector 33 is
As described below, data signal D from an external device is handled in the same way as when it is selected in the normal mode. However, during read access, the test data signal TD selected by the selector 33 is treated as reference data for checking memory errors in the RAM arrays 10-13.

First, in the case of write access in the test mode, the test data signal TD selected by the selector 33 is transferred to the RAM array 10 to 1 specified by the test address signal TA selected by the selector 32.
3 (banks #0 to #3) at the same address at the same time. This write access is for RAM arrays 10 to 13.
The process is performed in order from address 0 to the final address at a constant cycle. As a result, each address of RAM arrays 10 to 13 has R
If all of the AM arrays 10 to 13 are normal, the same data (test data signal TD) is written.

When the series of write accesses in the test mode described above is completed, the test control circuit 21 switches the test function signal TF from the write access designation state to the read access designation state, and sets the test mode signal TM to "1" (high). level). At this time, the test bank signal TB supplied from the test control circuit 21 to the bank switching circuit 23 is kept at a high level (all banks designated state) as in the write access designated state (in the test mode). Also, the test control circuit 21
Similarly to the write access designation state (in the test mode), the test address generator 26 sequentially generates test address signals TA from address 0 to the final address.

As a result of the above, all the RAM arrays 10 to 13 (banks #0 to #3) are selected by the bank switching circuit 23 in accordance with the high level test bank signal TB. Read access to addresses is performed in order from address 0 to the final address. Then, for each read access, the RAM array 10~
13, data signals (read data) at the same address (intra-bank address) specified by the test address signal TA are read out simultaneously.

Now, the select signal SEL from the test control circuit 21 is maintained at a high level ("1") during a series of read accesses in the test mode as well as during the write access described above. Therefore, also during the read access period in the test mode, the test data signal TD generated by the test data generator 27 is selected by the selector 33.

The test data signal TD selected by the selector 33 is supplied to the comparison circuit 25. This comparison circuit 25 is also supplied with data read simultaneously from the same address in the RAM arrays 10-13. Comparison circuit 2
5 operates in response to a high-level test mode signal TM applied from the test control circuit 21 during a series of read accesses in the test mode. and comparison circuit 25
compares each read data from the same address of the RAM arrays 10 to 13 with the test data signal TD selected by the selector 33 to detect coincidence/mismatch, and Outputs a bit match/mismatch detection signal.

Now, if the data at the address specified by the test address signal TA, which is simultaneously read out from the RAM arrays 10 to 13, is correct, the data at the address specified by the test address signal TA is read out from the selector 3.
It should match the test data signal TD selected by No. 3. Therefore, by detecting coincidence/mismatch through comparison by the comparator circuit 25, it is possible to notify whether or not there is a memory error in each of the RAM arrays 10 to 13.

The 4-bit match/mismatch detection signal (output signal) from the comparison circuit 25 is supplied to the status register 34 as an error notification signal. This status register 34 is also supplied with a test address signal TA selected by the selector 32. This test address signal TA is (if a mismatch is detected by the comparison circuit 25 during read access in the test mode)
, is held in the status register 34 together with the output signal (error notification signal) of the comparison circuit 25. The external device reads the contents of the status register 34 of the main memory device as a status signal ST, thereby controlling the RAM arrays 10 to 13.
You can check the error status.

In the above embodiment, the test data generator 27 generates fixed test data (test data signal TD).
), but the invention is not limited to this. For example, test data (test data determined by the test address signal TA) corresponding to the test address signal TA generated by the test address generator 26 may be generated. That is, the test data generator 27 is an adder that adds a constant value to the test address signal TA generated by the test address generator 26, or an adder that sequentially increments a certain initial value in synchronization with the operation of the test address generator 26. Alternatively, it may be a counter that decrements.

Furthermore, the test address signal TA generated by the test address generator 26 may be used as it is as the test data signal TD. That is, as shown in FIG. 2, the output of the test address generator 26 (test address signal TA) is converted into the test data signal T.
D may be connected to the "1" side input of the selector 33, and the test address signal TA (test data signal TD) may be selected by the selector 33 during the test mode. In this case, the test data generator 27 becomes unnecessary.

Further, in the above embodiment, the case where the number of RAM arrays and the number of memory banks are four each has been described, but it is needless to say that the present invention is not limited to this. Also,
The number of RAM arrays and the number of memory banks do not necessarily have to match.

Furthermore, in the above embodiment, the case where the storage section is constituted by one memory board has been explained, but the present invention is applicable to a memory test of a main memory device whose storage section is constituted by a plurality of memory boards. is also applicable. In this case, each memory board is provided with a comparison circuit 25 and a status register 34, but other circuits,
For example, the test control circuit 21, RAM control circuit 22, bank switching circuit 23, address switching circuit 24, test address generator 26, test data generator 27, and selectors 31 to 33 can be shared and mounted on multiple memory boards. It is possible to perform a memory test of each RAM array group in the same time as a memory test of one memory board. In addition, in the case of the main storage device shown in FIG.
Address signal A from an external device in normal mode matches the main memory address, but in the case of a main memory device whose storage unit is composed of multiple memory boards, address signal A is the lower part of the main memory address. is used, and the remaining upper part is used for a signal to specify one of the memory boards.

Furthermore, in the above embodiment, a case has been described in which the status register 34 is used to hold status information when a mismatch (error) is detected by the comparison circuit 25, but it is also possible to store a plurality of pieces of status information. It is also possible to use, for example, a ring buffer (circular buffer) or a register file. In this case, there is no possibility that the status information that has already been collected will be rewritten by the status information that is collected subsequently, which is convenient for grasping the error status of the entire RAM arrays 10 to 13. In addition, when using the status register 34, the RAM arrays 10 to 11 can be configured by interrupting the external device every time an error is detected and having the external device read the contents of the status register 34 each time.
It is also possible to grasp the error status of the entire 3.

Furthermore, in the above embodiment, banks #0 to #3
The explanation has been made assuming that read accesses are performed for all addresses in banks #0 to #3 after write accesses are completed for all addresses in banks #0 to #3. may be executed continuously.

Further, in the above embodiment, the case where the memory test was performed on the main memory device was explained, but the present invention can be applied to general memory tests on the memory devices included in information processing equipment.

[0049]

[Effects of the Invention] As detailed above, according to the present invention,
When a test mode is set for a storage device that has storage units configured with multiple memory banks in response to an external test request, all memory banks are selected, and operations that access the same location in each bank at the same time are For addresses, write access and read access are automatically performed in the order of write access, data written during write access and read from each bank during read access, and internally generated test data that should originally match the same data. Since the configuration is such that a memory error is detected by being compared by the comparator circuit, the following effects can be obtained.

(1) The test program can be simplified,
You can easily test storage devices. (2) Memory tests can be performed automatically within the storage device in response to external test requests, so external read/write
Test time can be reduced compared to the conventional method that performs memory tests sequentially by writing. (3) Since the same location of a plurality of memory banks can be accessed and checked at the same time, the test time remains the same even if the number of banks increases, and memory tests can be made even faster. (4) The time required for a memory test of a storage device consisting of multiple memory boards is the same as the time spent on one board, since the memory test can be performed on all memory boards simultaneously. In the case of large capacity, the test time can be significantly reduced compared to the conventional method. (5) Can be realized with a small number of test circuits.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of a main memory device to which a memory test method of the present invention is applied.

FIG. 2 is a block diagram showing another embodiment of the invention.

[Explanation of symbols]

10-13...RAM array, 21...Test control circuit, 2
2...RAM control circuit, 23...Bank switching circuit, 25...Comparison circuit, 26...Test address generator, 27...Test data generator, 31-33...Selector, 34...Status register, R...Request signal, F...Function Signal, T...Test signal, A...Address signal, D...Data signal, ST...Status signal, TR...Test request signal, TF...Test function signal, TB...Test bank signal, TM...Test mode signal, TA...Test address signal, TD...data signal for test.

Claims (2)

[Claims] Claim 1: In a memory test method for a storage device having a storage unit consisting of a plurality of memory banks configured by a RAM array, a test signal for requesting a memory test is applied from the outside to change the mode from a normal mode to a test mode. A test control circuit that controls the memory test by switching to the memory test, and a test address generation circuit that generates test addresses in a fixed order for each write access and read access for all addresses in the bank under the control of this test control circuit. a test data generator that generates preset fixed test data or generates test data corresponding to each address of the bank in a fixed order in synchronization with the operation of the test address generator; In response to an access request from the device using the storage device in mode, and in response to an access request from the test control circuit in test mode, the RAM array control circuit controls read/write to the RAM array; A bank switching circuit controls the switching of the banks according to an access request from the device, and selects all banks under the control of the test control circuit in the test mode. The test address generated by the test address generator is
A first selector that selects an address for accessing the M array, and a first selector that selects write data provided from the usage device in the normal mode, and test data generated by the test data generator in the test mode, into the RAM.
a second selector that selects data to be written to the array; and data read from each bank in accordance with the designation of the address selected by the first selector during read access in test mode; and the second selector. A comparison circuit for detecting a match/mismatch by comparing the data selected by the above, and a status holding means for holding error status information including the address at that time in response to the detection of a mismatch by the comparison circuit. 1. A memory test method, comprising: a memory test of a RAM array constituting a storage section of a storage device within the storage device in response to a test signal from the outside. 2. In a memory test method for a storage device having a storage section consisting of a plurality of memory banks constituted by a RAM array, a test signal for requesting a memory test is applied from the outside to change the mode from a normal mode to a test mode. A test control circuit that controls the memory test by switching to the memory test, and a test address generation circuit that generates test addresses in a fixed order for each write access and read access for all addresses in the bank under the control of this test control circuit. a RAM array control circuit that controls read/write to the RAM array in response to an access request from a device using the storage device in the normal mode, and an access request from the test control circuit in the test mode; In the mode, switching of the banks is controlled by the access request from the usage device, in the test mode, the bank switching circuit selects all banks under the control of the test control circuit, and in the normal mode, the address given from the usage device is controlled. In the test mode, a first selector selects the test address generated by the test address generator as the address for accessing the RAM array, and in the normal mode, the write data given from the utilization device is selected in the test mode. A second selector that selects the test address generated by the test address generator as data to be written to the RAM array, and a designation of the address selected by the first selector during read access in test mode. a comparison circuit for respectively comparing the data read from each bank and the data selected by the second selector in response to detecting a match/mismatch; and a status holding means for holding error status information including the address at that time, and performs a memory test of a RAM array constituting the storage section of the storage device within the storage device in response to an external test signal. A memory test method characterized by: