JPH04247771A - Horizontal synchronizing signal separator - Google Patents

Abstract

PURPOSE:To surely and stably separate a horizontal synchronizing signal by adding a signal resulting from inverting the polarity of a television input signal and delaying the signal to the input signal to cancel the fluctuation of a DC component. CONSTITUTION:An input television signal S1 is inverted by an inversion circuit 11, inputted to a delay circuit 12, in which the signal is delayed by a set prescribed time and a signal S3 is obtained. The signal S3 and the input signal S1 are added by an adder circuit 13 to generate a signal S4 and it is compared with a reference level by a comparator circuit 14 controlled by a signal Sc from a control circuit 15 and a horizontal synchronizing signal Sh is obtained. The control signal Sc is generated by an operation control circuit 15 in response to the horizontal synchronizing signal Sh. Thus, the horizontal synchronizing signal is stably separated without effect of fluctuation in the DC component.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal synchronizing signal separator for separating and detecting horizontal synchronizing signal components from television signals.

0002

2. Description of the Related Art As shown in FIG. 3, a conventional horizontal synchronizing signal separator includes a low-pass filter 31 that cuts off high-frequency components from an input television signal, and compares the level of the input signal with a predetermined reference value. and a comparison circuit 32 for detecting a synchronization signal component.

FIG. 4 is a waveform diagram showing an example of the operation. When a television signal S1 as shown in FIG. 4(A) is input, the output signal S2 of the low-pass filter 31 is as follows.
As shown in FIG. 4(B), the high frequency components are removed, resulting in a waveform consisting of horizontal synchronizing signal components. The comparison circuit 32 compares the level of the output signal S2 of the low-pass filter 31 with the level of the output signal S2 shown in FIG.
B) By comparing with the reference level Vs shown in FIG. 4(C), a horizontal synchronizing signal SH is output as shown in FIG. 4(C).

0004

[Problems to be Solved by the Invention] In the conventional horizontal synchronizing signal separator described above, when the DC component of the input television signal S1 fluctuates as shown in FIG. 5(A), the output signal of the low-pass filter 31 changes. As shown in FIG. 5(B), S2 changes in accordance with fluctuations in the DC component. For this reason,
When the comparator circuit 32 detects the horizontal synchronizing signal by comparing it with the reference level, there are cases where the level of the horizontal synchronizing signal fluctuates and cannot be detected, resulting in a problem that synchronization separation cannot be performed normally.

SUMMARY OF THE INVENTION An object of the present invention is to provide a horizontal synchronizing signal separator that can normally separate and detect a horizontal synchronizing signal even if the DC component of an input television signal fluctuates.

[0006]

[Means for Solving the Problems] A horizontal synchronizing signal separator of the present invention includes: an inverting circuit for inverting the polarity of an input television signal; a delay circuit for delaying an output signal of the inverting circuit; and an output signal of the delay circuit; a comparison circuit that operates in response to a control signal and compares the output signal of the addition circuit with a predetermined reference value to detect a horizontal synchronization signal component; and an operation control circuit that generates the control signal in synchronization with the horizontal synchronization signal component output from the circuit. Further, the delay time of the delay circuit is set within the horizontal synchronization period of the television signal, and furthermore, the control signal starts operating at least before the delay time when the horizontal synchronization signal arrives, and the control signal starts operating at least before the delay time when the horizontal synchronization signal arrives, and The comparator circuit is configured to control the comparator circuit so as to stop its operation at the same time as the signal is detected.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, which includes an inverting circuit 11 for inverting the polarity of an input television signal S1, a delay circuit 12 for providing a delay time Td, and an inverting circuit 11 for inverting the polarity of an input television signal S1. An adder circuit 13 that adds the output signal S3 of the delay circuit 12, and a control signal Sc.
a comparator circuit 14 that operates according to the output signal S4 of the adder circuit 13 and generates a horizontal synchronization detection signal Sh by comparing the output signal S4 of the adder circuit 13 with a reference level; and an operation control circuit that generates a control signal Sc that controls the operation of the comparator circuit 14. 15.

Next, the operation will be explained. FIG. 2 is a waveform diagram showing an example of the operation of this embodiment. First, an input television signal S1 as shown in FIG.
The polarity is inverted by Td by the delay circuit 12.
The signal S3 is delayed by a certain amount, resulting in a signal S3 having a waveform as shown in FIG. 2(B). The delay time Td is set within the horizontal synchronization period, for example, 4 μs. This signal S3 and input television signal S1
are added in the adder circuit 13, resulting in a signal S4 having a waveform as shown in FIG. 2(C). This signal S4 is compared with a reference level Vs by a comparison circuit 14 whose operation is controlled by a control signal Sc, and outputs a horizontal synchronization detection signal Sh having a waveform as shown in FIG. 2(E).

By the way, the operation control circuit 15 generates a control signal Sc in response to the horizontal synchronization detection signal Sh output from the comparison circuit 14. This control signal Sc is shown in FIG.
), it remains at the "H" level for a certain period of time Tc, which is set slightly shorter than the period of the horizontal synchronizing signal.
When it receives the horizontal synchronization detection signal Sh when it is at the "L" level, it becomes the "H" level again. The comparison circuit 14 stops operating when the control signal Sc is at the "H" level, and starts operating when the control signal Sc is at the "L" level.

[0011] Now, consider a case where the DC component of the input television signal S1 fluctuates. The change occurred in Figure 2.
This is the period from T4 to T8. The output signal S3 of the delay circuit 12 is delayed by Td with respect to the input television signal S1 and is an inverted signal, as shown in FIG. 2(B). Now, time T3 when the DC component does not fluctuate
, and the levels of the input television signal S1 at the time T5 when the DC component fluctuated are V1 and V2, it means that the DC component has fluctuated by (V2 - V1). Furthermore, the level of the output signal S3 of the delay circuit 12 at time points T3 and T5 is reversed in polarity to -V
1 , −V2, so V2 −(−V1 )=(
This means that the DC component has fluctuated by V1 - V2). When these two signals are added by the adder circuit 13, they cancel each other out, so the output signal S4 of the adder circuit 13 does not include DC fluctuations.

[0012] Also, T1 to T2, T2 to T3,
T4 to T5, T6 to T7, T7 to T8, T
Each level VT1, VT2, VT4, VT of the output signal S4 of the adder circuit 13 in each period of 8 to T9
6, VT7, VT8 are VT1=V3 +(-V1
) = V3 - V1 ... (1)
VT2=V1+(-V3)=V1-V3=
-VT1...(2) VT4=V2 +(-V
1)=V2-V1...(3
) VT6=V4 +(-V2)=V4-V2
...(4) VT7=V2
+(-V4)=V2-V4
...(5) VT8=V1 +(-V4)=V
1 −V2 = −VT4 (6). Here, V4 = V3 + (V2 - V1)...
(7) Therefore, equation (7) can be transformed into equations (4) and (5).
Substituting into, VT6=V3 -V1 =VT1
...(8) VT7=V1 -
V3 = -VT1 = VT2 (9), and the same signal level as in the case where no fluctuation of the DC component occurs is obtained.

Now, the comparator circuit 13 compares the level of the signal S4 with a preset reference level Vs,
An "L" level signal is output when the level is below the reference level Vs. In this case, as shown in FIG. 2(D), the control signal Sc becomes "H" level during the period Tc and the operation of the comparator circuit 13 is stopped, so the output signal S of the adder circuit 13 is
4 Level fluctuations occurring in VT2, VT4, VT7, V
T8 etc. are not detected. In addition, the control signal Sc becomes "L" level slightly before the arrival of the horizontal synchronization signal and puts the comparator circuit 14 into the operating state, but when the horizontal synchronization signal is detected, it becomes "H" level again, so that E) A horizontal synchronization detection signal Sh synchronized with the horizontal synchronization signal as shown in FIG.

[0014]

As explained above, the horizontal synchronizing signal separator of the present invention inverts the polarity of an input television signal using an inverting circuit, delays this polarity-inverted television signal using a delay circuit, and The output signal of the input television signal is added to the input television signal in an adder circuit to generate a signal that cancels out the variation in the DC component, and the comparison circuit detects the horizontal synchronization signal, thereby eliminating the fluctuation in the DC component of the input television signal. Horizontal synchronization signals can be detected without being affected by In addition, the delay time in the delay circuit is set within the horizontal synchronization period of the television signal, and an operation control circuit is provided to control the operation of the comparator circuit so that the operation starts at least the delay time before the arrival of the horizontal synchronization signal. By starting the horizontal synchronizing signal and stopping the operation at the same time as detecting the horizontal synchronizing signal, the horizontal synchronizing signal can be reliably and stably detected without being affected even if the DC component of the input television signal fluctuates.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram showing an example of the operation of this embodiment.

FIG. 3 is a block diagram showing an example of a conventional horizontal synchronization signal separator.

FIG. 4 is a waveform diagram showing an example of the operation of a conventional horizontal synchronizing signal separator.

FIG. 5 is a waveform diagram showing an example of the operation of a conventional horizontal synchronizing signal separator.

[Explanation of symbols]

11 Inversion circuit 12 Delay circuit 13 Adder circuit 14 Comparison circuit 15 Operation control circuit S1 Input television signal Sh Horizontal synchronization detection signal Sc Control signal

Claims (2)

[Claims] 1. An inversion circuit that inverts the polarity of an input television signal, a delay circuit that delays an output signal of the inversion circuit, and an addition circuit that adds the television signal and the output signal of the delay circuit. , a comparison circuit that operates according to a control signal and detects a horizontal synchronization signal component by comparing the output signal of the adder circuit with a predetermined reference value; A horizontal synchronizing signal separator comprising: an operation control circuit that generates a control signal. 2. A delay time of the delay circuit is set within a horizontal synchronization period of the television signal, and the control signal starts operating at least before the delay time when the horizontal synchronization signal arrives, A horizontal synchronizing signal separator, characterized in that the comparator circuit is controlled to stop operating at the same time as detecting the horizontal synchronizing signal.