JPH0424793U - - Google Patents
Info
- Publication number
- JPH0424793U JPH0424793U JP6625190U JP6625190U JPH0424793U JP H0424793 U JPH0424793 U JP H0424793U JP 6625190 U JP6625190 U JP 6625190U JP 6625190 U JP6625190 U JP 6625190U JP H0424793 U JPH0424793 U JP H0424793U
- Authority
- JP
- Japan
- Prior art keywords
- personal computer
- signal output
- reset
- analog
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Details Of Television Scanning (AREA)
- Color Television Systems (AREA)
Description
図は本考案の一実施例を示すスキヤン周波数変
換回路のブロツク図である。
３は書き込み／読み出しそれぞれ独立したクロ
ツク／リセツト入力可能なフレームメモリ、１２
は波形整形器７、位相比較器８、フイルタ９、電
圧制御発振器１０、分周器１１からなるクロツク
信号発生部である。
The figure is a block diagram of a scan frequency conversion circuit showing an embodiment of the present invention. 3 is a frame memory capable of independent clock/reset input for writing/reading; 12
is a clock signal generating section consisting of a waveform shaper 7, a phase comparator 8, a filter 9, a voltage controlled oscillator 10, and a frequency divider 11.
Claims (1)
信号Ｒ，Ｇ，Ｂをアナログ／デイジタル変換器を
介して書き込み、読み出し、それぞれ独立したク
ロツク／リセツトの入力可能なスキヤン周波数変
換用フレームメモリに接続し、同フレームメモリ
の書き込みリセツト端子に前記パーソナルコンピ
ユータ出力の垂直同期信号を接続し、同フレーム
メモリの書き込みクロツク端子に前記パーソナル
コンピユータ出力の水平同期信号を基準周波数と
する書き込みクロツク発生部出力を接続し、同フ
レームメモリ入力の読み出しクロツク及びリセツ
トによるスキヤン周波数変換デイジタル映像信号
Ｒ，Ｇ，Ｂをデイジタル／アナログ変換器を介し
て映像信号出力回路に接続してなることを特徴と
するテレビ受像機。 Analog video signals R, G, and B output from a personal computer, etc. are written and read via an analog/digital converter, connected to a scan frequency conversion frame memory that can input independent clock/reset, and then The vertical synchronization signal output from the personal computer is connected to the write reset terminal, and the output of a write clock generator whose reference frequency is the horizontal synchronization signal output from the personal computer is connected to the write clock terminal of the same frame memory. 1. A television receiver characterized in that scan frequency converted digital video signals R, G, B based on a readout clock and reset are connected to a video signal output circuit via a digital/analog converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6625190U JPH0424793U (en) | 1990-06-21 | 1990-06-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6625190U JPH0424793U (en) | 1990-06-21 | 1990-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0424793U true JPH0424793U (en) | 1992-02-27 |
Family
ID=31598804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6625190U Pending JPH0424793U (en) | 1990-06-21 | 1990-06-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0424793U (en) |
-
1990
- 1990-06-21 JP JP6625190U patent/JPH0424793U/ja active Pending
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