JPH0427692B2 - - Google Patents

Info

Publication number
JPH0427692B2
JPH0427692B2 JP56197851A JP19785181A JPH0427692B2 JP H0427692 B2 JPH0427692 B2 JP H0427692B2 JP 56197851 A JP56197851 A JP 56197851A JP 19785181 A JP19785181 A JP 19785181A JP H0427692 B2 JPH0427692 B2 JP H0427692B2
Authority
JP
Japan
Prior art keywords
oxide film
silicon
silicon oxide
element isolation
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56197851A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5898935A (ja
Inventor
Kohei Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56197851A priority Critical patent/JPS5898935A/ja
Publication of JPS5898935A publication Critical patent/JPS5898935A/ja
Publication of JPH0427692B2 publication Critical patent/JPH0427692B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
JP56197851A 1981-12-09 1981-12-09 半導体装置の製造方法 Granted JPS5898935A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56197851A JPS5898935A (ja) 1981-12-09 1981-12-09 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56197851A JPS5898935A (ja) 1981-12-09 1981-12-09 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5898935A JPS5898935A (ja) 1983-06-13
JPH0427692B2 true JPH0427692B2 (cs) 1992-05-12

Family

ID=16381387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56197851A Granted JPS5898935A (ja) 1981-12-09 1981-12-09 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5898935A (cs)

Also Published As

Publication number Publication date
JPS5898935A (ja) 1983-06-13

Similar Documents

Publication Publication Date Title
EP0098687B1 (en) Method of manufacturing a semiconductor device including burying an insulating film
US4292156A (en) Method of manufacturing semiconductor devices
JPS6359251B2 (cs)
US5371036A (en) Locos technology with narrow silicon trench
US5397732A (en) PBLOCOS with sandwiched thin silicon nitride layer
JPS6174350A (ja) 半導体装置の製造方法
JP2875972B2 (ja) 半導体素子の隔離方法
JP2896072B2 (ja) 半導体素子のフィールド酸化膜の形成方法
US6194319B1 (en) Semiconductor processing method of reducing an etch rate of one portion of a doped material relative to another portion, and methods of forming openings
JPH0917780A (ja) 半導体装置の素子分離膜の形成方法
JPH0427692B2 (cs)
JP2822211B2 (ja) 半導体装置の製造方法
US6245643B1 (en) Method of removing polysilicon residual in a LOCOS isolation process using an etching selectivity solution
JPS6213047A (ja) 半導体装置の製造方法
KR940009578B1 (ko) 반도체 장치 및 그 제조방법
JPS62232143A (ja) 半導体装置の製造方法
KR0167674B1 (ko) 반도체 소자의 소자분리막 형성방법
JPH0458538A (ja) 半導体装置の製造方法
JPS60127741A (ja) 半導体装置の製法
JPS6248028A (ja) フイ−ルド酸化膜の形成方法
JPH04240748A (ja) 半導体装置の製造方法
JPS6339103B2 (cs)
JPS6152980B2 (cs)
JPS6324635A (ja) 半導体装置の製造方法
JPH021916A (ja) 分離酸化膜の形成方法