JPH04280514A - Phase locked loop employing voltage controlled oscillator - Google Patents
Phase locked loop employing voltage controlled oscillatorInfo
- Publication number
- JPH04280514A JPH04280514A JP3043130A JP4313091A JPH04280514A JP H04280514 A JPH04280514 A JP H04280514A JP 3043130 A JP3043130 A JP 3043130A JP 4313091 A JP4313091 A JP 4313091A JP H04280514 A JPH04280514 A JP H04280514A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- controlled oscillator
- control voltage
- amplifier
- loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims abstract description 18
- 238000001514 detection method Methods 0.000 claims abstract description 18
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 18
- 230000007423 decrease Effects 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は電圧制御発振器の位相同
期ループに関し、特に電圧制御発振器の前段に直流増幅
器を有し、位相同期ループがロック状態になるまでは高
速に応答し、ロックすると周波数安定度を高めるように
動作する電圧制御発振器の位相同期ループに関する。[Industrial Application Field] The present invention relates to a phase-locked loop of a voltage-controlled oscillator, and in particular, it has a DC amplifier in the front stage of the voltage-controlled oscillator, and responds quickly until the phase-locked loop becomes locked. The present invention relates to a phase-locked loop of a voltage controlled oscillator that operates to enhance stability.
【0002】0002
【従来の技術】従来、この種の電圧制御発振器の位相同
期ループは、例えば図2に示すように、制御電圧VCが
0V近辺で所定の周波数で発振する電圧制御発振器21
と、制御電圧VCを出力する直流増幅器22と、ループ
フィルタ23と、電圧制御発振器の出力信号と基準信号
との位相を比較する位相比較器24とを備えている。2. Description of the Related Art Conventionally, as shown in FIG. 2, for example, a phase-locked loop of this type of voltage controlled oscillator is a voltage controlled oscillator 21 which oscillates at a predetermined frequency when the control voltage VC is around 0V.
, a DC amplifier 22 that outputs a control voltage VC, a loop filter 23, and a phase comparator 24 that compares the phase of the output signal of the voltage controlled oscillator and the reference signal.
【0003】ここで、直流増幅器22の入出力特性は、
図3に示すように、入力電圧が0Vから離れるにしたが
って増幅度が増大し、また、0V近辺では増幅度が急激
に減少するように非線形とする。このような特性とする
ことにより、位相同期ループがアンロック状態のときは
、制御電圧VCが0Vから離れるので増幅度が増大して
ループゲインも増大し、ロック状態への引込みが強化さ
れ応答速度は高速になる。一方、ロック状態に近付くに
つれて、つまり0Vに近付くにつれて増幅度が減少して
ループゲインも減少するので、ループの雑音帯域幅が狭
くなり周波数的に安定する。[0003] Here, the input/output characteristics of the DC amplifier 22 are as follows:
As shown in FIG. 3, the amplification degree increases as the input voltage moves away from 0V, and is nonlinear so that the amplification degree sharply decreases near 0V. With such characteristics, when the phase-locked loop is in the unlocked state, the control voltage VC moves away from 0V, so the degree of amplification increases and the loop gain also increases, which strengthens the pull-in to the locked state and improves the response speed. becomes faster. On the other hand, as the lock state approaches, that is, as the voltage approaches 0V, the amplification degree decreases and the loop gain also decreases, so the noise bandwidth of the loop narrows and becomes stable in terms of frequency.
【0004】0004
【発明が解決しようとする課題】上述した従来の電圧制
御発振器の位相同期ループでは、電圧制御発振器の前段
に接続する直流増幅器の特性を、入力電圧が0Vから離
れるにしたがって増幅度が増大し、また、0V近辺では
増幅度が急激に減少する非線形となるようにしている。
しかし、このような直流増幅器の回路構成は複雑になる
ばかりでなく、調整も面倒であるという問題点を有して
いる。In the phase-locked loop of the conventional voltage controlled oscillator described above, the characteristics of the DC amplifier connected before the voltage controlled oscillator are such that as the input voltage moves away from 0V, the degree of amplification increases. Furthermore, the amplification level is nonlinear in that the degree of amplification rapidly decreases near 0V. However, the circuit configuration of such a DC amplifier is not only complicated, but also has problems in that adjustment is troublesome.
【0005】本発明の目的は、簡単な回路構成により、
ロック状態になるまでは高速に応答し、ロックすると周
波数安定度を高めるように動作する電圧制御発振器の位
相同期ループを提供することにある。[0005] An object of the present invention is to
An object of the present invention is to provide a phase-locked loop of a voltage controlled oscillator that responds at high speed until it reaches a lock state and operates to improve frequency stability when it locks.
【0006】[0006]
【課題を解決するための手段】本発明の電圧制御発振器
の位相同期ループは、制御電圧が0V近辺で位相同期し
て所定の周波数で発振する電圧制御発振器と、前記制御
電圧を出力する直流増幅器と、前記制御電圧が0Vを中
心とした所定の微小範囲内にあるか否かを検知する電圧
検知回路と、この電圧検知回路の検知出力に応じてオン
オフ動作するスイッチ回路と、このスイッチ回路の動作
に応じて前記直流増幅器の出力端から入力端への帰還量
を変化させる帰還用抵抗とを備え、前記制御電圧が前記
所定の微小範囲内にあるときは前記直流増幅器の増幅度
を減少させ、前記制御電圧が前記所定の微小範囲の外に
あるときは前記直流増幅器の増幅度を増大させるように
構成されている。[Means for Solving the Problems] A phase-locked loop of a voltage-controlled oscillator of the present invention includes a voltage-controlled oscillator that oscillates at a predetermined frequency in phase synchronization when a control voltage is around 0V, and a DC amplifier that outputs the control voltage. a voltage detection circuit that detects whether the control voltage is within a predetermined minute range centered around 0V; a switch circuit that operates on and off according to the detection output of this voltage detection circuit; and a feedback resistor that changes the amount of feedback from the output end to the input end of the DC amplifier according to the operation, and reduces the amplification degree of the DC amplifier when the control voltage is within the predetermined minute range. , the amplification degree of the DC amplifier is increased when the control voltage is outside the predetermined minute range.
【0007】[0007]
【実施例】次に本発明について図面を参照して説明する
。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【0008】図1は本発明の一実施例を示すブロック図
であり、制御電圧VCが0V近辺で所定の周波数で発振
する電圧制御発振器11と、制御電圧VCを出力する演
算増幅器12と、ループフィルタ13と、電圧制御発振
器の出力信号と基準信号との位相を比較する位相比較器
14と、制御電圧VCが所定範囲にあることを検知する
電圧検知回路15と、スイッチ回路16と、帰還用抵抗
17,18とを備えている。FIG. 1 is a block diagram showing an embodiment of the present invention, which includes a voltage controlled oscillator 11 that oscillates at a predetermined frequency when the control voltage VC is around 0V, an operational amplifier 12 that outputs the control voltage VC, and a loop. A filter 13, a phase comparator 14 that compares the phase of the output signal of the voltage controlled oscillator and a reference signal, a voltage detection circuit 15 that detects that the control voltage VC is within a predetermined range, a switch circuit 16, and a feedback circuit. It is equipped with resistors 17 and 18.
【0009】ここで、電圧検知回路15は、制御電圧V
Cが0Vを中心とした所定の微小範囲内のときに検知信
号SCを送出する。スイッチ回路16は検知信号SCを
受けるとオン状態となる。演算増幅器12は、帰還用抵
抗17,18によって負帰還量を制御され増幅度を変化
させる。Here, the voltage detection circuit 15 detects the control voltage V
A detection signal SC is sent out when C is within a predetermined minute range centered around 0V. The switch circuit 16 is turned on upon receiving the detection signal SC. The operational amplifier 12 has a negative feedback amount controlled by feedback resistors 17 and 18 to change the amplification degree.
【0010】次に動作を説明する。Next, the operation will be explained.
【0011】位相同期ループがアンロック状態のとき、
すなわち、制御電圧VCが0Vから離れているとき、検
知信号SCは送出されないので、スイッチ回路16はオ
フ状態である。従って、演算増幅器12の出力側から入
力側への帰還は、帰還用抵抗17を介して行われるが、
帰還量が少ないので、演算増幅器12の増幅度は大きく
ループゲインも増大する。つまり、ロック状態への引込
みは強く、応答速度は高速となる。一方、ロック状態に
近付いて制御電圧VCが0Vを中心とした所定の微小範
囲に入ると、電圧検知回路15が検知信号SCを送出し
、スイッチ回路16はオン状態となり、帰還用抵抗17
,18が並列に接続されるので、帰還量は増大して演算
増幅器12の増幅度は減少し、ループゲインも減少して
ループの雑音帯域幅が狭くなり周波数的に安定する。[0011] When the phase-locked loop is in the unlocked state,
That is, when the control voltage VC is far from 0V, the detection signal SC is not sent out, so the switch circuit 16 is in an off state. Therefore, feedback from the output side of the operational amplifier 12 to the input side is performed via the feedback resistor 17.
Since the amount of feedback is small, the amplification degree of the operational amplifier 12 is large and the loop gain is also increased. In other words, the locking state is strong and the response speed is fast. On the other hand, when the lock state is approached and the control voltage VC enters a predetermined minute range centered around 0V, the voltage detection circuit 15 sends out a detection signal SC, the switch circuit 16 turns on, and the feedback resistor 17
, 18 are connected in parallel, the amount of feedback increases, the amplification degree of the operational amplifier 12 decreases, the loop gain also decreases, the noise bandwidth of the loop is narrowed, and the frequency becomes stable.
【0012】なお、演算増幅器12の増幅度が変化した
ときに制御電圧VCの変化が最小となるように、電圧検
知回路15は、0Vを中心とした十分に狭い範囲を検知
するように設定する。Note that the voltage detection circuit 15 is set to detect a sufficiently narrow range centered around 0V so that the change in the control voltage VC is minimized when the amplification degree of the operational amplifier 12 changes. .
【0013】[0013]
【発明の効果】以上説明したように本発明の電圧制御発
振器の位相同期ループは、0V近辺で所定の周波数で発
振する電圧制御発振器の制御電圧を検知し、制御電圧が
0Vを中心とした所定の微小範囲外にあるときは、この
制御電圧を出力する演算増幅器の増幅度を増大させてル
ープゲインを増大させ、また、制御電圧が0Vを中心と
した所定の微小範囲内にあるときは、演算増幅器の増幅
度を減少させてループゲインを減少させることにより、
簡単な回路構成によって、位相同期ループがロック状態
になるまは高速に応答し、ロックすると周波数安定度を
高めるように動作させることができる。As explained above, the phase-locked loop of the voltage-controlled oscillator of the present invention detects the control voltage of the voltage-controlled oscillator that oscillates at a predetermined frequency near 0V, and the control voltage is controlled at a predetermined frequency around 0V. When the control voltage is outside the minute range, the amplification of the operational amplifier that outputs this control voltage is increased to increase the loop gain, and when the control voltage is within a predetermined minute range centered around 0V, By reducing the amplification of the operational amplifier and reducing the loop gain,
With a simple circuit configuration, it is possible to operate the phase-locked loop to respond quickly until it is locked, and to improve frequency stability once locked.
【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
【図2】従来の電圧制御発振器の位相同期ループの一例
を示すブロック図である。FIG. 2 is a block diagram showing an example of a phase-locked loop of a conventional voltage controlled oscillator.
【図3】図2に示した直流増幅器22の入出力特性を示
す図である。3 is a diagram showing input/output characteristics of the DC amplifier 22 shown in FIG. 2. FIG.
11,21 電圧制御発振器
12 演算増幅器
15 電圧検知回路16
スイッチ回路17,18 帰還用抵抗11, 21 Voltage controlled oscillator 12 Operational amplifier 15 Voltage detection circuit 16
Switch circuit 17, 18 Feedback resistor
Claims (1)
定の周波数で発振する電圧制御発振器と、前記制御電圧
を出力する直流増幅器と、前記制御電圧が0Vを中心と
した所定の微小範囲内にあるか否かを検知する電圧検知
回路と、この電圧検知回路の検知出力に応じてオンオフ
動作するスイッチ回路と、このスイッチ回路の動作に応
じて前記直流増幅器の出力端から入力端への帰還量を変
化させる帰還用抵抗とを備え、前記制御電圧が前記所定
の微小範囲内にあるときは前記直流増幅器の増幅度を減
少させ、前記制御電圧が前記所定の微小範囲の外にある
ときは前記直流増幅器の増幅度を増大させることを特徴
とする電圧制御発振器の位相同期ループ。1. A voltage controlled oscillator that oscillates at a predetermined frequency in phase synchronization with a control voltage around 0V, a DC amplifier that outputs the control voltage, and a DC amplifier that outputs the control voltage within a predetermined minute range centered around 0V. a voltage detection circuit that detects whether or not the voltage is present, a switch circuit that operates on and off according to the detection output of this voltage detection circuit, and feedback from the output terminal of the DC amplifier to the input terminal according to the operation of this switch circuit. and a feedback resistor that changes the amount of feedback, the amplification degree of the DC amplifier is reduced when the control voltage is within the predetermined minute range, and when the control voltage is outside the predetermined minute range. A phase locked loop for a voltage controlled oscillator, characterized in that the amplification degree of the DC amplifier is increased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3043130A JPH04280514A (en) | 1991-03-08 | 1991-03-08 | Phase locked loop employing voltage controlled oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3043130A JPH04280514A (en) | 1991-03-08 | 1991-03-08 | Phase locked loop employing voltage controlled oscillator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04280514A true JPH04280514A (en) | 1992-10-06 |
Family
ID=12655266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3043130A Pending JPH04280514A (en) | 1991-03-08 | 1991-03-08 | Phase locked loop employing voltage controlled oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04280514A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6516001B1 (en) | 1998-06-05 | 2003-02-04 | Nec Corporation | Device for converting sonet data input into DS-N data output |
| JP2005184544A (en) * | 2003-12-19 | 2005-07-07 | Matsushita Electric Ind Co Ltd | Synchronous clock generation apparatus and synchronous clock generation method |
-
1991
- 1991-03-08 JP JP3043130A patent/JPH04280514A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6516001B1 (en) | 1998-06-05 | 2003-02-04 | Nec Corporation | Device for converting sonet data input into DS-N data output |
| JP2005184544A (en) * | 2003-12-19 | 2005-07-07 | Matsushita Electric Ind Co Ltd | Synchronous clock generation apparatus and synchronous clock generation method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990622 |