JPH04317599A - Driving system for stepping motor - Google Patents

Abstract

PURPOSE:To prevent a step-out in a stepping motor for driving an imaging unit for a copying machine or the like. CONSTITUTION:The first driving circuit system is constituted of counters 2, 3, and the second driving circuit system is constituted of counters 4, 5. A CPU1 first gives dividing ratio of the first step and a pulse count number to the first driving circuit system and dividing ratio of the second step and a pulse count number to the second driving circuit system. First the output of the first driving circuit system is supplied to a motor driver and the output of the second driving circuit system is supplied to the motor driver when an interruption signal from the first driving circuit system is generated. At this time dividing ratio of the third step and a pulse count number is repeatedly given to the first driving circuit system.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading device used in a copying machine and the like, and more particularly to a method for driving a stepping motor that drives an imaging unit.

0002

2. Description of the Related Art An image reading device used in a copying machine or the like is equipped with an imaging unit for reading an image of a document. As imaging units, there are known ones that include only an optical system for irradiating a document, and ones that include a contact type sensor.

[0003] The imaging unit is generally driven by a stepping motor, in which case a speed profile as shown in FIG. 2 is adopted. In FIG. 2, A is a period during which image reading is performed, B is a return period, C and F are speed increase periods, D and G are constant speed periods, and E
, H indicate the deceleration period. The speed increase and deceleration are set so that the acceleration is constant.

FIG. 3 is a diagram showing a configuration example of a stepping motor drive circuit conventionally used to achieve the speed profile shown in FIG. 2, and its operation is shown in FIG.
Explain with reference to.

Now, the counter 32 is given the frequency division ratio RD1 from the CPU 31, and the counter 33 is given the frequency division ratio RD1 from the CPU 31.
Assuming that a pulse count number PC1 is given from , the counter 32 divides the clock CLK by a frequency division ratio RD1 and outputs the pulses obtained by frequency division to the motor driver 34. This drives the stepping motor 35. At this time, the output pulse of the counter 32 is also
3 is input. The counter 33 converts the output pulses of the counter 32 into a pulse count number P given from the CPU 31.
When only C1 is counted, an interrupt signal I is sent to the CPU 31.
Notify NT. Then, the CPU 31 controls the counter 33
When receiving the interrupt signal INT from , the next step (
The frequency division ratio DR2 of T2) is given to the counter 32, and the pulse count number PC2 is given to the counter 33. Note that the frequency of the clock signal CLK is approximately 12 MHz. Further, the times of each step indicated by T1, T2, T3, T4, . . . in FIG. 4 are all set equally.

[0006] By repeating the above operations,
The speed profile shown in FIG. 2 is realized. Furthermore, Figure 4
It is clear to those skilled in the art that the frequency division ratio DR and pulse count number PC of each step are determined by the speed profile.

[0007]

In the configuration shown in FIG. 3, when the interrupt signal INT is input from the counter 33, the CPU 31 inputs the frequency division ratio DR and the pulse count number to the counters 32 and 33, respectively. Set the PC, but after the interrupt signal INT is input, the division ratio D
The time allowed before setting R, pulse count number PC is the time of half a cycle of pulses required in the next step. For example, when moving from step T2 to step T3 in FIG. 4, DR3 and PC3 must be set within the first half period of the first pulse of step T3, as indicated by t0 in the figure. If this is not the case, the counter 32 will no longer be able to output pulses of a predetermined form, and the stepping motor 35 will step out.

By the way, the frequency of the pulses output from the counter 32 during the period when the imaging unit shown by D in FIG. 2 is driven at the highest speed is required to be about 13.8 kHz, and in order to achieve this speed, The CPU 31 waits approximately 36 μs after the step of the constant speed period starts.
During ec, the frequency division ratio CR and pulse count PC required for the step must be set in the counters 32 and 33, respectively.

[0009] On the other hand, as the CPU 31, a general-purpose 8-bit CPU is often used for the purpose of ease of use or cost reduction. The number of instructions that can be executed in a given time is about 24. And C
The PU31 does not operate independently, but is connected to other CPU3.
6. For example, in a copying machine, communication is performed with the main CPU etc. to exchange necessary information, and this CPU
Communication between them is given a higher priority than the interrupt signal INT from the counter 33. Because the CPU
This is because if communication between the two cannot be performed normally, correct image recording will not be possible.

Therefore, if an interrupt signal INT is sent from the counter 33 while communicating with another CPU 36, or if a communication request is made from the CPU 36 while the interrupt signal INT is being sent, ,
Since the CPU 31 prioritizes communication processing with the CPU 36, there is no time to set the frequency division ratio DR and the pulse count number PC, resulting in a problem that the stepping motor 35 loses synchronization.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a stepping motor drive method that can effectively prevent step-out of the stepping motor.

0012

[Means and operations for solving the problems] In order to achieve the above object, the stepping motor drive system of the present invention includes two drive circuit systems, a first drive circuit system and a second drive circuit system. The output of these two drive circuit systems is alternately taken out for each step of changing the speed of the stepping motor.

That is, counter 2 and counter 3 constitute a first drive circuit system, and counter 4 and counter 5 constitute a second drive circuit system. The CPU 1 first gives the first step frequency division ratio and pulse count number to the first drive circuit system, and gives the second step frequency division ratio and pulse count number to the second drive circuit system. Then, first, the output of the first drive circuit system is supplied to the motor driver,
When an interrupt signal is generated from the first drive circuit system, the signal system is switched so that the output of the second drive circuit system is supplied to the motor driver, and the CPU 1 sends the first drive circuit system to the third step. Give the frequency division ratio and pulse count number.

By repeating the above operations, step-out of the stepping motor can be prevented.

[0015]

Embodiments Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of a stepping motor driving system according to the present invention. In the figure, 1 is a CPU, 2, 3, 4, 5 are counters, and 6, 7, 8 are AN
D circuit, 9 and 10 are OR circuits, 11 is a flip-flop (hereinafter referred to as FF), and 12 is a NOT circuit.

The counter 2 divides the clock CLK by the frequency division ratio DRA given from the CPU 1, and the counter 3 converts the output pulses of the counter 2 outputted via the AND circuits 6 and 7 into a pulse count given from the CPU 1. Number P
When CA is counted, an interrupt signal INTA is sent to CPU1.

Similarly, the counter 4 divides the clock CLK by the frequency division ratio DRB given from the CPU 1, and the counter 5 converts the output pulses of the counter 4 outputted via the AND circuit 8 into a pulse count given from the CPU 1. Number P
After counting CB, it sends an interrupt signal INTB to CPU1.

That is, the configuration shown in FIG. 1 includes two systems of conventional stepping motor drive circuits shown in FIG. 3.

Next, the operation of FIG. 1 will be explained with reference to FIG. 4.

[0021] Now, the main CPU (not shown in FIG. 1)
When an instruction to start reading is given from , the CPU 1 sets the frequency division ratio DR1 and the pulse count number PC in step T1.
1 is set in counter 2 and counter 3, respectively, and the frequency division ratio DR2 and pulse count number PC2 of step T2 are set in counter 4 and counter 5, respectively, and the start signal STR is sent to AND circuit 6, and FF11
A set signal SET is given to . Thereby, the output pulse of the counter 2 is supplied to a motor driver (not shown in FIG. 1) via the AND circuits 6 and 7 and the OR circuit 9. At this time, the Q output of the FF 11 is sent to the AND circuit 8.
Since it is inverted and inputted by the OT circuit 12, the output of the counter 4 does not pass through the AND circuit 8. Furthermore, FF1
1 assumes that the Q output becomes high level when the set signal SET is applied.

When the counter 3 counts the output pulses of the counter 2 by the number given by the pulse count PC1, it outputs an interrupt signal INTA. This interrupt signal INTA is passed through the OR circuit 10 to the FF1
Since the Q output of the FF 11 is inverted, the AND circuit 7 is closed and the AND circuit 8 is opened. Therefore, the clock CLK is frequency-divided by the frequency division ratio DR2 by the counter 4 and supplied to the motor driver.

The interrupt signal INTA is also input to the CPU 1 at the same time. As a result, the CPU 1 recognizes that the operation of the first drive circuit system consisting of counters 2 and 3 has been completed, and sets the frequency division ratio DR at step T3.
3 and pulse count number PC3 are given to counter 2 and counter 3, respectively.

Next, the counter 5 calculates the pulse count number P
After counting the output pulses of the counter 4 by the number given by C2, it outputs an interrupt signal INTB. As a result, the Q output of the FF 11 is inverted, the AND circuit 8 is closed, the AND circuit 7 is opened, and the output of the counter 2 is supplied to the motor driver. At this time, the CPU 1 recognizes that the operation of the second drive circuit system consisting of the counter 4 and the counter 5 is completed, and sets the counters 4 and 5 to perform the next step of frequency division T4. Ratio DR4
and the pulse count number PC4 is given.

The above operations are repeated.

The operation of the imaging unit when speeding up has been described above, but the same applies when decelerating.

Although one embodiment of the present invention has been described above, it is clear that the present invention is not limited to the above embodiment and that various modifications can be made.

[0028]

As is clear from the above description, according to the present invention, while one drive circuit system is operating, that is, during one step, the CPU 1 has no control over the other drive circuit system. All you need to do is set the frequency division ratio and pulse count number.
Furthermore, since the period of one step is approximately 3 msec, there is sufficient margin even if the CPU 1 communicates with other CPUs. Therefore, step-out of the stepping motor can be effectively prevented, and a predetermined speed profile can be reliably achieved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of a stepping motor driving method according to the present invention.

FIG. 2 is a diagram showing a speed profile of an imaging unit.

FIG. 3 is a diagram showing a configuration example of a conventional stepping motor drive circuit.

FIG. 4 is a diagram showing an example of driving pulses for a stepping motor.

[Explanation of symbols]

1...CPU, 2,3,4,5...Counter, 6,7,8...
AND circuit, 9, 10...OR circuit, 11...FF, 12...
NOT circuit.

Claims (1)

[Claims] 1. A first counter that divides a clock signal by a frequency division ratio set by a control means and outputs the divided clock signal to a stepping motor drive means; and a count that sets the number of output pulses of the first counter to a count set by the control means. Stepping comprising two sets of driving means each including a second counter that generates an interrupt signal to the control means when the number of pulses is counted, and output pulses from the two sets of driving means are taken out alternately. Motor drive method.