JPH0432527U - - Google Patents
Info
- Publication number
- JPH0432527U JPH0432527U JP1990073688U JP7368890U JPH0432527U JP H0432527 U JPH0432527 U JP H0432527U JP 1990073688 U JP1990073688 U JP 1990073688U JP 7368890 U JP7368890 U JP 7368890U JP H0432527 U JPH0432527 U JP H0432527U
- Authority
- JP
- Japan
- Prior art keywords
- view
- utility
- contact
- outer edge
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
第１〜３図は本考案の一実施例を示すもので、
第１図は平面図、第２図は要部拡大断面図、第３
図は要部拡大側面図である。第４〜６図は従来の
ＩＣを示す図であり、第４図は平面図、第５図は
要部拡大断面図、第６図は要部拡大側面図である
。
１……チツプ、４……ボンデイングパツド、５
……チツプ外辺。
Figures 1 to 3 show an embodiment of the present invention.
Figure 1 is a plan view, Figure 2 is an enlarged sectional view of main parts, and Figure 3 is a plan view.
The figure is an enlarged side view of the main part. 4 to 6 are views showing a conventional IC, with FIG. 4 being a plan view, FIG. 5 being an enlarged sectional view of the main part, and FIG. 6 being an enlarged side view of the main part. 1... Chip, 4... Bonding pad, 5
...Outside of the chip.
Claims (1)
辺に接して設けたことを特徴とする半導体素子。 A semiconductor device characterized in that a plurality of bonding pads are provided in contact with the outer edge of a semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990073688U JPH0432527U (en) | 1990-07-11 | 1990-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990073688U JPH0432527U (en) | 1990-07-11 | 1990-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0432527U true JPH0432527U (en) | 1992-03-17 |
Family
ID=31612724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990073688U Pending JPH0432527U (en) | 1990-07-11 | 1990-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0432527U (en) |
-
1990
- 1990-07-11 JP JP1990073688U patent/JPH0432527U/ja active Pending