JPH04325876A - Pulse generator - Google Patents

Abstract

PURPOSE:To obtain an output pulse signal in which a pulse width is varied at a high speed. CONSTITUTION:Initial data when a pulse width is varied, is set to an incremental-decremental counter 1a by a microprocessor. Then, final data is set to a data comparator 1c. The counter 1a incrementally or decrementally counts by a data comparator 1b until the output data coincides with set data. The incremental or decremental data of this case is sequentially latched to a buffer 1b. Data to be set to a counter 1 is continuously updated by using the latched data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator used to obtain a pulse width modulated output pulse signal for controlling a discharge lamp lighting circuit.

0002

[Prior Art] A pulse generator used to obtain a pulse width modulated output pulse signal for controlling a discharge lamp lighting circuit uses a microprocessor, and a predetermined value is determined by an internal counter formed by software according to a program. There is a device that obtains output pulse signals of on and off duty (predetermined "H" section and "L" section).

However, in such a pulse generator, the setting accuracy of on/off duty is regulated by the machine cycle of the microprocessor, and since the machine cycle is generally about several μsec,
There is a problem in that the on/off duty cannot be set with an accuracy of less than c, which is a problem when used as a pulse generator for switching control of a discharge lamp lighting circuit that lights a discharge lamp at a high frequency.

[0004] Therefore, the "H" section setting data and "L" section setting data of the output pulse signal are latched in a data latch circuit, a clock signal of a constant period is counted, and a preset is established in which the above two section setting data are set alternately. The ripple carry signal from the double counter circuit is used as the trigger clock signal of the toggle flip-flop circuit, and a pulse width modulated output pulse signal is obtained from the toggle flip-flop circuit. "Interval and"
The on/off duty setting accuracy is not restricted by the microprocessor's machine cycle, as would be the case if the "L" section was set, and the "H" section and "L" section are set regardless of the machine cycle. A pulse generator has been proposed in which the interval can be arbitrarily set and the on/off duty setting accuracy can be increased.

[0005]

However, in the above-described pulse generator, if new data is not output from the microprocessor within one cycle of the pulse width modulated output pulse signal, the next cycle will also be the same as the previous cycle. Output pulse signals with the same pulse width are output. Therefore, in the case of an output pulse signal with a pulse width smaller than the machine cycle of the microprocessor, new data cannot be output from the microprocessor within one cycle, and as shown in Figure 13, the pulse width is the same as the previous cycle. The output pulse signal will be output multiple times. In other words, the conditions for generating an output pulse signal whose pulse width is changed every cycle are related to the ability of the microprocessor. In order to deal with this problem, it is possible to use a high-speed microprocessor, but even that has its limits. For example, even the current fastest microprocessor has 40MHz
It is before and after the z clock. Moreover, such microprocessors are expensive and therefore impractical.

The present invention has been made in view of the above points, and its object is to provide a pulse generator that can change the pulse width at high speed.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a pulse width control means that independently changes "H" section setting data and "L" section setting data of an output pulse signal. The above-mentioned two section setting data are set, and the final data of the up-down counter circuit is set by the up-down counter circuit that counts up or down the above-mentioned section setting data, and the above-mentioned pulse width control means, and the final data of the up-down counter circuit is set by the above-mentioned pulse width control means. A data comparison circuit that counts until the output count data matches the final data, a buffer that latches the count data of the up/down counter circuit, and the latch data of this buffer is set alternately for each section setting data. This includes a presettable counter circuit that counts using a clock signal of a constant period, and a toggle flip-flop circuit that uses the ripple carry signal of this counter circuit as a trigger clock to create a pulse width modulated output pulse signal.

[0008]

[Operation] By configuring as described above, the pulse width control means sets the initial data for changing the pulse width in the up/down counter circuit, and sets the final data in the data comparison circuit. The counter circuit can update the data set in the presettable counter circuit by up-counting or down-counting regardless of the microprocessor's machine cycle, making it possible to change the pulse width at high speed. be.

[0009]

Embodiment FIGS. 1 to 12 show an embodiment of the present invention. The pulse generator of this embodiment has an output pulse signal of “H”.
an up/down counter circuit 1a which is set with the above-mentioned section setting data given from a pulse width control means that changes the "section setting data" and "L" section setting data independently, and counts up or down the section setting data; , a data comparison circuit 1c in which the final data of the up/down counter circuit 1a is set by the pulse width control means, and counts are performed until the count data outputted from the up/down counter circuit 1a matches the final data; A buffer 1b that latches the count data of the down counter circuit 11, and a presettable counter circuit 2 that latches the count data of the down counter circuit 11 and that the latch data of this buffer 1b is set alternately for each interval setting data and counts with a clock signal CLK of a constant period.
and the ripple carry signal R from the counter circuit 2.
The toggle flip-flop circuit 3 uses CY1 as a trigger clock.

The pulse width control means is formed by a microprocessor, and "H" is used as initial data when changing the pulse width output from the microprocessor.
” section setting data and "L" section setting data are input terminals IN1 to IN of the up/down counter circuit 1a.
12, and is latched by a timing signal generated by the data comparison circuit 1c. In addition, "H" section setting data and "L" are used as final data when changing the pulse width output from the microprocessor.
The section setting data is input to the input terminal I1 of the data comparison circuit 1c.
~I12, and is latched by the timing signal output from the timing control circuit 4.

The up/down counter circuit 1a, buffer 1b and data comparison circuit 1c form a data latch circuit 1.
As shown in FIG. 2, the up/down counter circuit 1a has a 12-bit configuration using three 4-bit up/down counters UDC for each section setting data. Note that this up/down counter UDC is shown in Figure 3.
The configuration shown in is used. Further, the buffer 1b is formed of a flip-flop SFR and a tri-state buffer TBUF, as shown in FIG.

In the up/down counter circuit 1a, when the section data setting signal HL is input, the DT1 to DT input through the input terminals IN1 to IN12 is input to the up/down counter circuit 1a.
12 is set to "L" by the latch signals LATCHA and LATCHB, and the section setting data DA1 to DA12,
The data comparison circuit 1c latches the section setting data DB1 to DB12 as "H" section setting data, and the section setting data input to the input terminals I1 to I12 following this section setting data is latched by the latch signals LATCHA and LATCHB. In addition, in the secondary buffer 1b, the latch data DA1 to DA12,
Take in DB1 to DB12 and send enable signal EN
Section setting data DA selected by A,ENB
1 to DA12 or DB1 to DB12 are output as preset data for the counter circuit 2. In addition, the half clock control signal HLF is also latched once and the signal HAL is
It is output as F. Note that this half-clock control is a control that allows the "H" period and the "L" period to be arbitrarily set regardless of the machine cycle of the microprocessor, and a detailed explanation thereof will be given later.

The counter circuit 2 and the toggle flip-flop circuit 3 are integrated as a counter/output circuit 5, and as shown in FIG. 6, the 12-bit counter circuit 2 is constructed by using three 4-bit presettable counters CNT.
The ripple carry signal RCY1 of the counter circuit 2 is outputted to the toggle flip-flop circuit 3 via the half clock control circuit 6 as a ripple carry signal RCY as a trigger clock.

The flip-flop output of the toggle flip-flop circuit 3 is outputted as an output pulse signal OUT via two inverters, and at the same time an enable signal E for reading predetermined preset data from the data latch circuit 1 is output.
Output as NA and ENB. The half clock control circuit 6 is configured such that the half clock control signal HALF is “H”.
”, the rise of the ripple carry signal RCY1 (the inversion timing of the toggle flip-flop circuit) is shifted to the right by half a clock, and the clock signal C
It is possible to set the “H” and “L” intervals with half-clock precision (double precision) of LK. The timing control circuit 4 outputs latch signals LATCH and LATCH.
The latch control circuit 4a shown in FIG. 7 generates A, LATCHB, and LTCH, and the latch control circuit 4a shown in FIG. 8 generates a clear signal CLEAR, a load signal LOAD, and a latch signal LTCH1.
It is formed of a counter control circuit 4b shown in FIG. 4, and outputs a predetermined timing signal based on the clock signal CLK, start signal START, and section data setting signal HL output from the microprocessor to control the operation timing of each circuit. do.

By the way, in this type of pulse generator,
Two-phase clock signal OU based on output pulse signal OUT
A switching signal is used to determine whether to output the output pulse signal OUT or the two-phase clock signals OUT1 and OUT2 as output signals for controlling the switching of the two-phase clock generation circuit 7 that generates T1 and OUT2 and the discharge lamp lighting circuit 10. An output switching circuit 8 that is switched by SE/HB is provided, and is a single-ended type (output pulse signal OU
A discharge lamp lighting circuit 10 of a single-stone inverter type in which a switching transistor is controlled by T or a half-bridge type (a two-stone inverter type in which a pair of switching transistors connected in series are controlled by two-phase clock signals OUT1 and OUT2). A switching control signal is available.

Here, the two-phase clock generation circuit 7 includes a presettable counter circuit 7a that counts the clock signal CLK and sets a non-overlapping period, and a ripple carry signal RCY2' outputted from the presettable counter circuit 7a. A two-phase clock signal in which a non-overlapping section is set based on non-overlapping section setting data HB1 to HB8, which is formed by a gate control circuit 7b that controls a gate circuit 7c based on the 8-bit setting switch. It is designed to output OUT1 and OUT2.

The overall operation of the pulse generator will be explained below. Note that the following explanation is based on the up/down count of the up/down counter circuit 1a and the data comparison circuit 1c.
A case will be explained in which the data latch circuit 1 is prohibited by the following and is simply used as a primary buffer of the data latch circuit 1. Note that this can be done by setting the same section setting data in the up/down counter circuit 1a and the data comparison circuit 1c.

First, as shown in FIG. 10, when the start signal START output from the microprocessor rises, a system reset is performed. And “L”
” When the section setting data DA1 to DA12 is confirmed,
The section data setting signal HL rises from the microprocessor, one pulse of the latch signal LATCHA is output, and the up/down counter circuit 1a of the data latch circuit 1
"L" section setting data DA1 to DA12 are latched.

Next, "H" section setting data DB1
When ~DB12 is determined, one pulse of the latch signal LATCHB is output at the fall of the interval data setting signal HL, and the "H" interval setting data DB1 to DB12 are latched into the up/down counter circuit 1a of the data latch circuit 1. Then, the clear signal CLEAR is “L”
, one pulse of the latch signal LTCH is output, and both section setting data DA1 to DA12, DB1 to DB1 are output.
2 is latched into the secondary buffer 1b. At this time, since the enable signal ENA is "H", the "L" section setting data DA1 to DA is sent from the buffer 1b.
12 is read out and a load signal LOAD for setting preset data in the counter circuit 2 is output, the counter circuit 2 receives "L" section setting data DA1 to D.
A12 is set. In this state, the counter circuit 2 starts counting the clock signal CLK, and when the outputs Q1 to Q12 of the counter circuit 2 all become "H", the ripple carry signal RCY1 is output. This ripple carry signal RCY1 causes the enable signal ENB to become "H", and at the same time, the output pulse signal OUT also becomes "H". Then, the "H" section setting data DB1 to DB12 are preset in the counter circuit 2, the clock signal CLK starts counting, and when the ripple carry signal RCY1 is obtained, the output pulse signal becomes "L" and the enable signal EN is activated.
A becomes "H" and the above operation is repeated. Therefore, both section setting data DA1 to DA12, DB1
～Based on DB12, the output pulse signal OUT is “L”
" section and "H" section can be set arbitrarily (within a range of 12 bits), and on/off duty can be set. Furthermore, when changing on/off duty, "L" section setting data DA1 ~D
After setting A12, set the section data setting signal HL to “H”.
” and “H” Section setting data DB1 to DB12
After setting the section data setting signal HL to “L”
You should do it.

For example, as shown in FIG. 10, the frequency of the clock signal CLK is set to 16 MHz (period 62.5 ns).
c) Set the “H” section to 161 pulses, “L”
When setting the interval to 164 pulses, select “H”
Set the 8th bit and 6th bit of section setting data DA1 to DA12 to "1", and set the 8th bit and 6th bit of section setting data DB1 to DB12 to "L".
It is sufficient to set the second bit and the first bit to "1". In this case, the period of the output pulse signal OUT is 325 pulses of the clock signal CLK, which is 20.
2μsec, frequency 49. It becomes 2kHz. Also, if the width of the "H" section or "L" section is widened by one pulse (62.5nsec),
The period is 326 pulses of the clock signal CLK, and the frequency is 49. It becomes 1kHz. Therefore, the "H" section or "L" section of the output pulse signal OUT is set to 62. It can be set in 5nsec increments, and can be set in 0.
The frequency can be controlled in 1 kHz increments, and when used as a switching control signal for a pulse generator, fine lighting control can be performed. In addition,
Clock signal CLK counted by counter circuit 2
It goes without saying that setting accuracy can be increased by increasing the frequency.

Next, half clock control will be explained based on FIG. 11. Now, the half clock control signal H
When ALF is “L”, ripple carry signal R
CY1 directly serves as the trigger clock for the toggle flip-flop circuit 3, and as shown in FIG. 11(b), the output pulse signal OUT is inverted in synchronization with the rise of the ripple carry signal RCY as the trigger clock.

On the other hand, when the half clock control signal HALF becomes "H", the rising edge of the ripple carry signal RCY1 is shifted to the right by half a clock, as shown in FIG. 11(a), and this shifted ripple carry signal RCY serves as a trigger clock for the toggle flip-flop circuit 3, and the inversion operation of the output pulse signal OUT is performed. Therefore, half clock control signal HLF is “H”
In the case of “H” section or “L” section,
Section setting data DA1 ~DA12, DB1 ~DB1
Compared to the case of Figure 11(b) set in 2, it can be made wider by half a clock of the clock signal CLK, and the setting accuracy of the "H" interval and "L" interval can be increased without increasing the frequency of the clock signal CLK. can be doubled.

Two-phase clock generation circuit 7 operates as follows. In other words, in this two-phase clock generation circuit 7, a presettable counter circuit 7a to which non-overlap interval setting data HB1 to HB8 is preset counts the clock signal CLK to set a non-overlap interval. , as shown in FIG. 12, a gate control signal for controlling the gate circuit 7c is formed based on the ripple carry signal RCY2' output from the presettable counter circuit 7a, and the gate circuit 7c is controlled by this gate control signal. Thus, two-phase clock signals OUT1 and OUT2 are formed by adding a non-overlapping section to the output pulse signal OUT.

Output pulse signal OUT and two-phase clock signals OUT1 and OUT2 generated as described above
is output via the output switching circuit 8, and the switching signal SE
When /HB is "H", output pulse signal OUT is output, and when switching signal SE/HB is "L", two-phase clock signals OUT1 and OUT2 are output. Therefore, by appropriately setting the switching signal SE/HB, it is possible to obtain a pulse generator compatible with the single-end type or half-bridge type discharge lamp lighting circuit 10.

The operation when changing the pulse width of the output pulse signal will be explained below. When changing the pulse width of the output pulse signal in this way, the microprocessor sets initial data for changing the pulse width in the up/down counter circuit 1a, and sets initial data for changing the pulse width in the data comparison circuit 1c. Set the final data. Here, when the section setting data as the final data is set in the data comparison circuit 1c, it is determined by comparing whether this setting data matches the data set in the up/down counter circuit 1a, and if they do not match, then From the data comparison circuit 1c to the up/down counter circuit 1
By applying up/down signals DNUP1 and DNUP2 for up-counting or down-counting to a, the output data of the up-down counter circuit 1a can be set to the setting data. Do this until it matches.

When up-counting or down-counting is performed in the up-down counter circuit 1a in this manner, new data is latched into the buffer 1b every time it is incremented or decremented.
This data is transmitted by enable signals ENA and ENB.
H" and is set in the counter circuit 2 every time the load signal LOAD is input to the counter circuit 2. From then on, it is set in the counter circuit 2 in the same way as described above until the output data of the up/down counter circuit 1a matches the setting data. The counter circuit 2 counts different data.The data comparison circuit 1c controls up-counting or down-counting of the up-down counter circuit 1a in synchronization with the updating of data in the counter circuit 2. Therefore, an output pulse signal whose pulse width changes continuously as shown in Fig. 4 is obtained from the toggle flip-flop circuit 3. In the case of Fig. 4, the "L" section setting data is fixed. H” Indicates the case where only the section setting data is changed, the initial data is “1” and the final data is “5”.
”. In this way, if the microprocessor sets the initial data for changing the pulse width in the up-down counter circuit 1a and sets the final data in the data comparison circuit 1c, the up-down counter circuit 1a
The data set in the presettable counter circuit 2 can be updated by up-counting or down-counting regardless of the machine cycle of the microprocessor, and the pulse width can be changed at high speed. When the output data of the up/down counter circuit 1a match, the above operation ends and the normal operation returns to using the above-mentioned up/down counter circuit 1a as a primary buffer. The present embodiment can be used to control the lighting of a discharge lamp in a transitional stage when switching the discharge lamp to a fully lit state, a completely unlit state, or a predetermined dimmed lighting state.

[0027]

[Effects of the Invention] As described above, the present invention provides a system in which both the above-mentioned interval setting data given from the pulse width control means that independently change the "H" interval setting data and the "L" interval setting data of the output pulse signal are set. The final data of the up-down counter circuit is set by the up-down counter circuit for up-counting or down-counting the section setting data and the pulse width control means, and the count data output from the up-down counter circuit is the final data. a data comparison circuit that counts until it matches, a buffer that latches the count data of the up/down counter circuit, and the latch data of this buffer is set alternately for each interval setting data and is counted using a constant cycle clock signal. The device is equipped with a presettable counter circuit that performs pulse width modulation, and a toggle flip-flop circuit that creates a pulse width modulated output pulse signal using the ripple carry signal of this counter circuit as a trigger clock. By setting the initial data for changing the pulse width in , and setting the final data in the data comparison circuit, the up/down counter circuit can count up or down regardless of the microprocessor's machine cycle, making it a presettable function. The data set in the counter circuit can be updated, and the pulse width can be changed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2(a) is a circuit diagram of an up/down counter circuit. (b) is an explanatory diagram showing a terminal arrangement of a 4-bit up/down counter used in the above.

FIG. 3 is a circuit diagram of a 4-bit up/down counter constituting the same.

FIG. 4 is an explanatory diagram of main operations.

FIG. 5(a) is a circuit diagram of a buffer. (b) is an explanatory diagram of the terminal arrangement of the flip-flop used in the above.

FIG. 6(a) is a circuit diagram of a counter/output circuit. (b) is an explanatory diagram showing the terminal arrangement of the counter used in the above. (c) is an explanatory diagram of the terminal arrangement of the flip-flop used in the above.

FIG. 7 is a circuit diagram of a latch control circuit.

FIG. 8 is a circuit diagram of a counter control circuit.

FIG. 9(a) is a circuit diagram of a two-phase clock generation circuit. (b) is an explanatory diagram showing the terminal arrangement of the counter used in the above. (c) is an explanatory diagram of the terminal arrangement of the flip-flop used in the above.

FIG. 10 is an explanatory diagram of the overall operation same as above.

FIG. 11 is an explanatory diagram of half clock control operation.

FIG. 12 is an explanatory diagram of the operation of the two-phase clock generation circuit.

FIG. 13 is an explanatory diagram of conventional problems.

[Explanation of symbols]

1a Up/down counter circuit 1b Buffer 1c Data comparison circuit 2 Counter circuit 3 Toggle flip-flop circuit

Claims (1)

[Claims] [Claim 1] Both section setting data given from a pulse width control means that independently changes the "H" section setting data and "L" section setting data of the output pulse signal are set, and the section setting data is updated. The final data of the up-down counter circuit is set by an up-down counter circuit that counts or down-counts, and the pulse width control means, and counting is performed until the count data output from the up-down counter circuit matches the final data. a data comparison circuit, a buffer that latches the count data of the up/down counter circuit, and a presettable counter circuit that sets the latch data of this buffer alternately for each interval setting data and counts with a clock signal of a constant cycle; A pulse generator comprising: a toggle flip-flop circuit that generates a pulse width modulated output pulse signal using the ripple carry signal of the counter circuit as a trigger clock.