JPH04333947A - I/o access control system for dual bus system - Google Patents

Abstract

PURPOSE:To efficiently perform access from each bus master to an input/output part (I/O) by unnecessitating complicated control such as the connection switch of the I/O or the others. CONSTITUTION:Concerning the I/O access control system for a dual bus system equipped with two shared buses B1 and B2, plural I/O 6-1 and 6-2 respectively connected to the shared buses and plural bus masters 1-1 and 1-2 enabling access to the respective shared buses, the respective bus masters 1-1 and 1-2 are equipped with processor parts 2-1 and 2-2, monitor circuits 3-1 and 3-1 to compare whether the I/O to be accessed by this processor part is same as the I/O under access through the shared bus at present or not, and two gate circuits 4-1 and 4-2/5-1 and 5-2 for bus access request signal to control the opening/ closing according to these monitor circuits, when the compared result of the monitor circuits shows the same I/O, the gate circuits are closed and when the compared result does not show the same I/O, the gate circuits are opened.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system comprising a microprocessor, and more particularly to an I/O access control method in a dual bus system comprising a plurality of microprocessors and a plurality of shared buses.

0002

[Prior Art] I in a conventional dual bus system
In the /O access control method, the I/O (input/output unit) is connected to only one of the dual buses, or the I/O
A switching circuit for connecting to either of the dual buses is connected to /O, and access is controlled by instructing which bus to connect to from the processor section.

0003

[Problem to be Solved by the Invention] In the conventional I/O access control method in a dual bus system, even if two bus masters attempt to access different I/Os, the bus is occupied by another bus master. There are disadvantages in that access is not possible, and each bus master must instruct which bus to connect the I/O to each time it accesses the I/O.

0004

[Means for Solving the Problems] The system of the present invention includes two shared buses, a plurality of input/output units (I/O) connected to each of the shared buses, and access to each of the shared buses. In an I/O access control scheme in a dual bus system having a plurality of possible bus masters, each said bus master has a processor section and said I/O that this processor section is trying to access and that is currently being accessed through said shared bus. a monitoring circuit for comparing whether or not the I/Os are the same, and two gate circuits for bus access request signals whose opening/closing is controlled by the monitoring circuit, and the comparison result of the monitoring circuit is The gate circuit is closed when the comparison results are the same, and the gate circuit is opened when the comparison results are not the same.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, bus masters 1-1, 1-2 and I/Os 6-1, 6-2 are connected to shared buses B1, B2, and bus masters 1-1, 1-2 are connected to bus masters 1-1, 1-2, respectively. Gate circuits 4-1, 4-2, 5-1, 5- for request signals
2. Monitoring circuit 3-1, 3-2, processor unit (CPU) 2
-1, 2-2. For example, if the processor section 2-2 attempts to access the I/O 6-2 while the processor section 2-1 is accessing the I/O 6-1 through the shared bus B1, the monitoring circuit 3-2 , compares the specified I/O address of the processor section 2-2 with the addresses on the shared buses B1 and B2, and if they are not the same address, opens the gate circuits 4-2 and 5-2 and transfers the address to the processor section 2-2. 2 is connected to the shared buses B1 and B2, and if the shared bus B2 is not used, the processor unit 2-2
I/O 6-2 can be accessed through I/O 2. Furthermore, when the processor unit 2-2 attempts to access the I/O 6-1, the monitoring circuit 3-2 compares the specified I/O address with the addresses of the shared buses B1 and B2, and determines whether they are the same address. If there is, it recognizes that another processor section is accessing, closes the gate circuits 4-2 and 5-2, and accesses the processor section 2-2.
The second bus request signal is prevented from being connected to the shared buses B1 and B2. After this, the processor section 2-1
After accessing the shared bus B, open the gate circuits 4-2 and 5-2 and transfer the bus request signal from the processor section 2-2 to the shared bus B.
1 and B2, and the processor section 2-2 can access the I/O 6-1 through either the shared bus B1 or B2.

[0007]

[Effects of the Invention] As explained above, according to the present invention, the I/O that each bus master attempts to access can be accessed by another bus master, or if the I/O is not in use, it can be connected to either bus. Each bus master can efficiently access I/O without the need for complicated control such as determining whether the bus is available or switching the I/O connection to another bus if the bus cannot be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

B1, B2 Shared bus 1-1, 1-2 Bus master 4-1, 4-2, 5-1, 5-2 Gate circuit 3
-1, 3-2 Monitoring circuit 2-1, 2-2 Processor section (CPU) 6-1,
6-2 I/O

Claims (1)

[Claims] 1. A dual bus comprising two shared buses, a plurality of input/output units (I/O) connected to each of the shared buses, and a plurality of bus masters that can access each of the shared buses. In an I/O access control method in a bus system, each of the bus masters includes a processor unit;
The I/O that this processor section is trying to access
and the I currently being accessed through the shared bus.
/O and 2 for bus access request signals, which are controlled to open and close by this monitoring circuit.
I/O access in a dual bus system, characterized in that the gate circuit is closed when the comparison results of the monitoring circuits are the same, and the gate circuit is opened when the comparison results are not the same. control method.