JPH04335709A - Latch circuit and a/d converter using same - Google Patents

Abstract

PURPOSE:To make a conversion time interval of the A/D converter constant by making a time from a change in a signal of a clock input terminal of the latch circuit till a change in a signal at a noninverting output terminal equal to a time till a signal at an inverting output terminal changes. CONSTITUTION:The latch circuit consists of two latch circuits 2A, 2B. An input signal 1 is inputted to a 1st latch circuit 2A and its inverting signal is inputted to a 2nd latch circuit 2B respectively. A clock signal 5 is inputted in common to the two latch circuits 2A, 2B. A time till a signal at an inverting output terminal 3B rises after a signal at a noninverting output terminal 3A rises and a time till a signal at an inverting output terminal 3A rises after a signal at an inverting output terminal 3B rises are set to T and then equal to each other. The trailing time interval of the signal is similarly T and equal. Then the A/D conversion time interval is made constant.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit that is used in a digital circuit and holds an input signal according to a clock signal, and an A/D converter that converts an analog signal into a digital signal.

0002

2. Description of the Related Art An example of a latch circuit according to the first prior art is shown in FIG.

This latch circuit consists of switches 8A, 8B and inverters 7A, 7B, 7C. The switches 8A and 8B are made up of an nMOS transistor and a pMOS transistor, as shown in FIG.

When the clock signal 5 is of negative logic, the switch 8A is in a conductive state and the switch 8B is in a cut-off state. Therefore, a signal equal to input signal 1 appears at the non-inverting output terminal 3A, and its inverted signal appears at the inverting output terminal 3B. This is the transparent state. When the clock signal 5 changes from negative logic to positive logic, switch 8A becomes cut off and switch 8B becomes conductive. therefore,
A signal equal to the logical value of input signal 1 when clock signal 5 changes appears at non-inverting output terminal 3A, and its inverted signal appears at inverting output terminal 3B. This is the holding state.

At this time, the operation timing of the latch circuit shown in FIG. 8 is as shown in FIG. 10. Here, the meanings of the symbols are as follows. TAH is the time from when the clock signal 5 changes from positive logic to negative logic when the input signal 1 is positive logic until the signal at the non-inverting output terminal 3A changes from negative logic to positive logic, and TAL is the input signal TBL is the time from when the clock signal 5 changes from positive logic to negative logic to when the signal at the non-inverting output terminal 3A changes from positive logic to negative logic when input signal 1 is negative logic. TBH is the time from when the clock signal 5 changes from positive logic to negative logic until the signal at the inverted output terminal 3B changes from positive logic to negative logic, and TBH is the clock signal 5 when input signal 1 is negative logic. T1H is the time from when the signal 5 changes from positive logic to negative logic until the signal at the inverting output terminal 3B changes from negative logic to positive logic, and T1H is the time from when the input of inverter 7B changes from positive logic to negative logic. T1L is the time from when the input of the inverter 7B changes from negative logic to positive logic until the output changes from positive logic to negative logic. Here, since the inverter 7B connects the inverting output terminal 3B and the non-inverting output terminal 3A, the signal at the non-inverting output terminal 3A changes after T1H or T1L after the signal at the inverting output terminal 3B changes. changes. Therefore, there is a relationship between these times as shown in (Equation 1), and generally TAH and TBH, TAL and TBL
are not equal to each other.

[0006]

[Math 1]

Next, an example of the configuration of an A/D converter according to the first prior art is shown in FIG. The latch circuit 10 has, for example, the same configuration as that in FIG. 8. The A/D converters 11A and 11B each A/D convert the analog signal 12 at the rising timing of the signal at the A/D conversion clock input terminal.

FIG. 10 shows the operation timing of FIG. 3. A
The /D converter 11A performs A/D conversion of the analog signal 12 at the rising edge of the signal at the non-inverting output terminal Q of the latch circuit 10, and the results are A1 and A2 in FIG. On the other hand A/D
The converter 11B performs A/D conversion on the analog signal 12 at the rising edge of the signal at the inverting output terminal QB of the latch circuit 10,
The results are B1 and B2. A/D converter 11A, 1
The period of A/D conversion of 1B is 2T, but Fig. 3
The circuit is an A/D conversion circuit that performs two A/D conversions during a time of 2T.
/D converter. The circuit in Figure 3 allows low-speed A/
Two D converters can be used to equivalently obtain one A/D converter that is twice as fast.

FIG. 9 shows an example of a master-slave type latch circuit according to the second prior art. This latch circuit consists of latch circuits 2A, 2C and an inverter 6. The latch circuits 2A and 2C have the same configuration as the latch circuit shown in FIG. 8, for example.

First, when the clock signal 5 is in positive logic, the latch circuit 2A is in a holding state and the latch circuit 2C is in a transparent state. Therefore, a signal having the same logic as input signal 1 appears at the non-inverting output terminal Q of the latch circuit 2C, but the signals appearing at the non-inverting output terminal 3A and the inverting output terminal 3B do not change from the previously held logic.

Next, when the clock signal 5 changes from positive logic to negative logic, the latch circuit 2A changes to a transparent state, and the latch circuit 2C changes to a holding state. Then, the non-inverting output terminal Q and the non-inverting output terminal 3 of the latch circuit 2C
A signal with the same logic as the input signal 1 when the clock signal 5 changes from positive logic to negative logic appears at A, and its inversion appears at the inverting output terminal 3B.

Further, when the clock signal 5 changes from negative logic to positive logic, the latch circuit 2A changes to a holding state, and the latch circuit 2C changes to a transparent state. Then, a signal having the same logic as input signal 1 appears at the non-inverting output terminal Q of the latch circuit 2C, but the signals appearing at the non-inverting output terminal 3A and the inverting output terminal 3B do not change.

That is, this master-slave type latch circuit holds the logic of the input signal 1 when the clock signal 5 changes from positive logic to negative logic until the clock signal 5 changes from positive logic to negative logic. do.

At this time, the operation timing of the latch circuit shown in FIG. 9 is as shown in FIG. 11. Here, the meanings of the symbols are the same as in the first conventional technique, and the relationship (Equation 1) also holds true. However, the relationship between the symbol and (Equation 1) is that the latch circuit 2
This is only related to A, and is not related to the latch circuit 2C.

Next, an example of the configuration of an A/D converter according to the second prior art is shown in FIG. The master-slave type latch circuit 13 has, for example, the same configuration as that in FIG. 9. The A/D converters 11A and 11B each A/D convert the analog signal 12 at the rising timing of the signal at the A/D conversion clock input terminal.

FIG. 11 shows the operation timing of FIG. 4. A
The /D converter 11A performs A/D conversion of the analog signal 12 at the rising edge of the signal at the non-inverting output terminal Q of the latch circuit 13, and the results are A1 and A2 in FIG. On the other hand A/D
The converter 11B performs A/D conversion on the analog signal 12 at the rising edge of the signal at the inverting output terminal QB of the latch circuit 13,
The results are B1 and B2. A/D converter 11A, 1
The period of A/D conversion of 1B is 2T, but in Fig. 4
The circuit is an A/D conversion circuit that performs two A/D conversions during a time of 2T.
/D converter. The circuit in Figure 4 allows low-speed A/
Two D converters can be used to equivalently obtain one A/D converter that is twice as fast.

[0017]

As mentioned above, the latch circuit of FIG. 8, which is the first conventional technique, uses the clock signal 5
There is a problem in that the time from when the signal falls to when the signal at the non-inverting output terminal 3A changes is different from the time from when the signal at the inverting output terminal 3B changes. This problem becomes particularly serious when input signal 1 and clock signal 5 are periodic signals. The case where the period of input signal 1 is twice the period of clock signal 5 will be described below. At this time, the operation timing is as shown in FIG. Here, T is the period of the clock signal 5, and TABX is the period after the signal at the non-inverting output terminal 3A rises to the inverting output terminal 3.
TBAX is the time from when the signal at the inverting output terminal 3B rises until the signal at the non-inverting output terminal 3A rises.
This is the time it takes for the signal to rise. Then TAB
X and TBAX can be expressed as shown in (Equation 2).

[0018]

[Math 2]

Here, using (Equation 1), TABX and T
The relationship with BAX is as shown in (Equation 3), and generally,
These two are different from each other.

[0020]

[Math 3]

Similarly, the time from the fall of the signal at the non-inverting output terminal 3A until the fall of the signal at the inverting output terminal 3B, and the time from the fall of the signal at the inverting output terminal 3B to the fall of the signal at the non-inverting output terminal 3A It is also different from the time it takes for the signal to fall.

Therefore, if there is a circuit 11A that starts operating at the rising timing of the signal at the non-inverting output terminal 3A of this latch circuit, and a circuit 11B that starts operating at the rising timing of the signal at the inverting output terminal 3B, Then, the time from when the circuit 11A starts operating until the circuit 11B starts operating is different from the time from when the circuit 11B starts operating until the circuit 11A starts operating. Therefore, although the circuit 11A and the circuit 11B operate alternately, there is a problem in that the two circuits do not start operating at regular intervals. Further, for example, if it is necessary to prohibit the circuits 11A and 11B from operating simultaneously, the operating times of the two circuits will be limited by TABX and TBAX, respectively. Therefore, there was a problem in that the operating time of at least one of the circuits 11A and 11B had to be made shorter than half the period 2T of the signal at the non-inverting output terminal 3A and the signal at the inverting output terminal 3B.

[0023] In the first conventional A/D converter,
As mentioned above, in FIG. 10, when the input signal 1 and the clock signal 5 are periodic signals, the A/D converter 1
1A performs A/D conversion, and then A/D converter 11B performs A/D conversion.
/D conversion time and A/D converter 11B
This is different from the time from when A/D conversion is performed until the A/D converter 11A performs A/D conversion. Therefore, A/D
There was a problem in that the A/D conversion by the converters 11A and 11B was not performed at regular intervals. Moreover, as a result, even if the analog signal 12 changes at a constant rate over time, the A/D conversion result does not change at a constant rate over time. Compared to an ideal A/D converter that performs D conversion at regular intervals, this A/D converter has a problem in that the A/D conversion results include errors.

As mentioned above, the master-slave type latch circuit of FIG. 9, which is the second conventional technique, uses the clock signal 5.
There is a problem in that the time from when the signal falls to when the signal at the non-inverting output terminal 3A changes is different from the time from when the signal at the inverting output terminal 3B changes. This problem becomes particularly serious when input signal 1 and clock signal 5 are periodic signals. The case where the period of input signal 1 is twice the period of clock signal 5 will be described below. At this time, the operation timing is as shown in FIG. Here, the meanings of the symbols are the same as in FIG. 10, and the relationships of (Equation 2) and (Equation 3) also hold true. Therefore, at this time, the same problem as above occurred.

[0025] In the second conventional A/D converter,
As described above, in FIG. 9, when the input signal 1 and the clock signal 5 are periodic signals, the A/D converter 11
After A performs A/D conversion, A/D converter 11B performs A/D conversion.
The time required to perform D conversion and the time required for A/D converter 11B to perform A/D conversion.
This is different from the time from when D conversion is performed until the A/D converter 11A performs A/D conversion. Therefore, there was a problem similar to that of the first conventional A/D converter.

The present invention was made as a result of research into the drawbacks of conventional latch circuits and A/D converters as described above. The time from when the clock signal changes until the signal at the inverting output terminal rises is equal to the time from when the clock signal changes to when the signal at the non-inverting output terminal falls, and the time from when the clock signal changes until the signal at the non-inverting output terminal falls is equal to the clock The purpose of the present invention is to provide a latch circuit in which the time from when a signal changes to when a signal at an inverted output terminal falls is equal, and an A/D converter using the latch circuit that performs A/D conversion at fixed time intervals. There is.

[0027]

[Means for Solving the Problems] A latch circuit according to claim 1 of the present invention comprises first and second latch circuits that are set in a transparent state or a holding state in response to a clock signal, and is configured to transmit an input signal to the first latch circuit. an input terminal of the circuit, an inverted signal of the input signal is input to the input terminal of the second latch circuit, and a clock signal is input to the clock signal input terminals of the first latch circuit and the second latch circuit. , said first
The output signal of the second latch circuit is a non-inverted output signal, and the output signal of the second latch circuit is an inverted output signal.

The master-slave type latch circuit according to claim 2 of the present invention comprises first, second and third latch circuits that become transparent or held in response to a clock signal, and passes an input signal to the third latch. The output signal of the third latch circuit is input to the input terminal of the first latch circuit, and the inverted signal of the output signal of the third latch circuit is input to the second latch circuit. A clock signal is input to the clock signal input terminal of the first latch circuit and the second latch circuit, and an inverted signal of the clock signal is input to the clock signal input terminal of the third latch circuit. The output signal of the first latch circuit is a non-inverted output signal, and the output signal of the second latch circuit is an inverted output signal.

The A/D converter according to claim 3 of the present invention includes:
The latch circuit includes the latch circuit of claim 1 and first and second A/D converters, and the same analog signal is transmitted to the first A/D converter.
The D converter performs A/D conversion at a timing given by the non-inverted output signal of the latch circuit, and converts the second A/D
The converter is characterized in that it performs A/D conversion at a timing given by the inverted output signal of the latch circuit.

The A/D converter according to claim 4 of the present invention includes:
The master-slave type latch circuit according to claim 2, and first and second A/D converters, wherein the first A/D converter receives the same analog signal and the non-inverted output signal of the latch circuit. A/D conversion is performed at the timing given by
The second A/D converter is characterized in that it performs A/D conversion at a timing given by the inverted output signal of the latch circuit.

[0031]

[Operation] In the latch circuit according to claim 1, with the above-described configuration, signals of opposite logical values are applied to the input terminals of the first and second latches, respectively, and signals of equal phase are applied to the clock input terminals. A clock signal is applied. If the two latch circuits have the same configuration, the operation delay times will be equal to each other, so the time from when the clock signal changes until the signal at the output terminal of the first latch circuit rises is equal to the time when the clock signal changes. This is equal to the time from when the signal at the output terminal of the second latch circuit rises. That is, the time from when the clock signal changes until the signal at the non-inverting output terminal rises is equal to the time from when the clock signal changes until the signal at the inverting output terminal rises. Similarly, the time from when the clock signal changes until the signal at the non-inverting output terminal falls is equal to the time from when the clock signal changes until the signal at the inverting output terminal falls.

In the master-slave type latch circuit according to the second aspect of the present invention, with the above-described configuration, signals of opposite logic values are applied to the input terminals of the first and second latches, respectively, and the clock input terminal has the following effects: Equal clock signals are applied to each. If the two latch circuits have the same configuration, the operation delay times will be equal to each other, so the time from when the clock signal changes until the signal at the output terminal of the first latch circuit rises is equal to the time when the clock signal changes. This is equal to the time from when the signal at the output terminal of the second latch circuit rises. That is, the time from when the clock signal changes until the signal at the non-inverting output terminal rises is equal to the time from when the clock signal changes until the signal at the inverting output terminal rises. Similarly, the time from when the clock signal changes until the signal at the non-inverting output terminal falls is equal to the time from when the clock signal changes until the signal at the inverting output terminal falls.

The A/D converter according to claim 3 has the above-described configuration, and as described above, the latch circuit according to claim 1 causes the signal at the non-inverting output terminal to rise after the clock signal changes. The time from when the clock signal changes until the signal at the inverting output terminal rises is equal to each other, and the time from when the clock signal changes until the signal at the non-inverting output terminal falls , and the time from when the clock signal changes until the signal at the inverting output terminal falls are equal to each other. Therefore, when the input signal and clock signal of this latch circuit are periodic signals, and the period of the input signal is twice the period of the clock signal, A an A/D converter that performs /D conversion;
A at the timing given by the signal of the inverted output terminal
An A/D converter that performs A/D conversion is an A/D converter that alternately converts A
/D conversion.

The A/D converter according to claim 4 has the above-described configuration, and as described above, in the master-slave type latch circuit according to claim 2, the signal at the non-inverting output terminal changes after the clock signal changes. The time from when the clock signal changes until the signal at the inverting output terminal rises is the same as the time from when the clock signal changes until the signal at the non-inverting output terminal falls. and the time from when the clock signal changes until the signal at the inverted output terminal falls are equal to each other. therefore,
It functions similarly to claim 3.

[0035]

Embodiment Embodiment 1 FIG. 1 shows an example of the configuration of a latch circuit according to claim 1 of the present invention.

This circuit consists of the first latch circuits 2A and 2B.
The inverter 4 generates an inverted signal of the input signal 1, which is applied to the input terminal D of the latch circuit 2B. The latch circuits 2A and 2B are equal in phase,
For example, it has the same configuration as the latch circuit shown in FIG.

First, when the clock signal is negative logic,
The latch circuits 2A and 2B become transparent. therefore,
A signal equal to input signal 1 appears at non-inverting output terminal 3A,
The inverted signal appears at the inverted output terminal 3B, and the latch circuit of FIG. 1 is in a transparent state.

Next, when the clock signal 5 changes to positive logic, the latch circuits 2A and 2B enter the holding state. Therefore, a signal equal to the logical value of the input signal 1 when the clock signal 5 changes appears at the non-inverting output terminal 3A, and its inverted signal appears at the inverting output terminal 3B, so that the latch circuit of FIG. 1 enters the holding state. .

The operation timing of the latch circuit shown in FIG. 1 is as shown in FIG. Here, the meanings of the symbols are as follows. In the latch circuits 2A and 2B, TAH is the time from when the clock signal 5 changes from positive logic to negative logic when the signal at the input terminal is positive logic until the signal at the output terminal changes from negative logic to positive logic. , TAL are latch circuits 2A, 2B
, it is the time from when the clock signal 5 changes from positive logic to negative logic when the signal at the input terminal is negative logic until the signal at the output terminal changes from positive logic to negative logic.

Then, a positive logic signal is applied to the input terminal 1, and the period from when the clock signal 5 changes from positive logic to negative logic until the signal at the non-inverting output terminal 3A changes from negative logic to positive logic. When a negative logic signal is applied to input terminal 1, what is the time from when clock signal 5 changes from positive logic to negative logic until the signal at inverted output terminal 3B changes from negative logic to positive logic? , both are TAH and are equal.

Similarly, a negative logic signal is applied to the input terminal 1, and the clock signal 5 changes from positive logic to negative logic until the signal at the non-inverting output terminal 3A changes from positive logic to negative logic. and the time from when a positive logic signal is applied to input terminal 1 and when clock signal 5 changes from positive logic to negative logic until the signal at inverting output terminal 3B changes from positive logic to negative logic. , both are TAL and are equal.

Furthermore, considering the case in which the input signal 1 and the clock signal 5 are periodic signals in the latch circuit of FIG. 1, and the period of the input signal 1 is twice that of the clock signal 5, The operation timing of the latch circuit shown in FIG. 1 is as shown in FIG.

[0043] Here, the meanings of the symbols are as follows. T is the period of the clock signal 5, TAB is the non-inverting output terminal 3
The time from the rise of the signal A to the rise of the signal at the inverting output terminal 3B, TBA is the time from the rise of the signal at the inverting output terminal 3B until the rise of the signal at the non-inverting output terminal 3A. Then, TAB and TBA are (
It can be expressed as in equation 4).

[0044]

[Math 4]

Therefore, the relationship between TAB and TBA is (
As shown in equation 5), they are equal.

[0046]

[Math 5]

Similarly, the time from the fall of the signal at the non-inverting output terminal 3A until the fall of the signal at the inverting output terminal 3B, and the time from the fall of the signal at the inverting output terminal 3B to the fall of the signal at the non-inverting output terminal 3A The time it takes for the signal to fall is T in both cases and is equal to each other. This solves the problems of the conventional technology.

(Embodiment 2) FIG. 2 shows an example of the configuration of a master-slave type latch circuit according to claim 2 of the present invention. This circuit consists of latch circuits 2A, 2B, 2C and inverters 4, 6. Inverter 4 creates an inverted signal of input signal 1, which is applied to the input terminal of latch circuit 2B. An inverted signal is created and applied to the clock signal input terminal of latch circuit 2C. The latch circuits 2A and 2B are equal in phase and have the same configuration as, for example, the latch circuit of FIG. 8. Latch circuit 2C
does not have to have the same configuration as 2A and 2B, but operates similarly.

First, when the clock signal 5 is in positive logic, the latch circuits 2A and 2B are in a holding state, and the latch circuit 2C is in a transparent state. Therefore, a signal having the same logic as input signal 1 appears at the non-inverting output terminal Q of the latch circuit 2C, but the signals appearing at the non-inverting output terminal 3A and the inverting output terminal 3B do not change from the previously held logic.

Next, when the clock signal 5 changes from positive logic to negative logic, the latch circuits 2A and 2B become transparent.
The latch circuits 2C each change to a holding state. Then, a signal with the same logic as the input signal 1 when the clock signal 5 changes from positive logic to negative logic appears at the non-inverting output terminal Q and the non-inverting output terminal 3A of the latch circuit 2C, and at the inverting output terminal 3B. The reversal appears.

Furthermore, when the clock signal 5 changes from negative logic to positive logic, the latch circuits 2A and 2B enter the holding state.
The latch circuits 2C each change to a transparent state. Then, a signal having the same logic as the input signal 1 appears at the non-inverting output terminal of the latch circuit 2C, but the signals appearing at the non-inverting output terminal 3A and the inverting output terminal 3B do not change.

That is, like the conventional master-slave type latch circuit shown in FIG. 9, this master-slave type latch circuit changes the logic of the input signal 1 when the clock signal 5 changes from positive logic to negative logic. It is held until the clock signal 5 changes from positive logic to negative logic.

At this time, the operation timing of the latch circuit of FIG. 2 is as shown in FIG. 6. Here, the meanings of the symbols are the same as in Example 1, and the relationships of (Equation 4) and (Equation 5) also hold true. However, the relationship between the symbols and (Equation 4) and (Equation 5) relates only to the latch circuits 2A and 2B, and does not relate to the latch circuit 2C.

[0054] Therefore, similar to the first embodiment, the problems of the prior art are solved. (Embodiment 3) FIG. 3 shows an example of the configuration of an A/D converter according to claim 3 of the present invention.

This configuration is similar to a conventional A/D converter, and the A/D converters 11A and 11B convert the analog signal 12 into A/D converters at the rising timing of the signal at the A/D conversion clock input terminal. The point of conversion is also the same, but
The difference is that the latch circuit 10 is the latch circuit of FIG.

FIG. 5 shows the operation timing of FIG. 3 at this time. The A/D converter according to claim 3 of the present invention operates in the same manner as a conventional A/D converter, and has a low speed A/D converter.
By using two A/D converters, one A/D converter with twice the speed is obtained. However, as described in the first embodiment, in FIG. 5, when the input signal 1 and the clock signal 5 are periodic signals, the A/D converter 11A performs A/D conversion and then the A/D converter The time it takes for 11B to perform A/D conversion,
This is equal to the time from when the A/D converter 11B performs A/D conversion until when the A/D converter 11A performs A/D conversion. Therefore, A by A/D converters 11A and 11B
/D conversion is performed at regular intervals. Further, for example, if the analog signal 12 changes at a constant rate with respect to time, the A/D conversion result also changes at a constant rate with respect to time, and the A/D conversion result does not include error. .

(Embodiment 4) FIG. 4 shows an example of the configuration of an A/D converter according to claim 4 of the present invention.

This configuration is similar to a conventional A/D converter, and the A/D converters 11A and 11B convert the analog signal 12 into A/D converters at the rising timing of the signal at the A/D conversion clock input terminal. The point of conversion is also the same, but
The difference is that the master-slave type latch circuit 13 is the master-slave type latch circuit of FIG.

FIG. 6 shows the operation timing of FIG. 4 at this time. The A/D converter according to claim 4 of the present invention operates in the same manner as a conventional A/D converter, and has a low speed A/D converter.
By using two A/D converters, one A/D converter with twice the speed is obtained. However, as described in the second embodiment, in FIG. 6, when the input signal 1 and the clock signal 5 are periodic signals, the A/D converter 11A performs A/D conversion and then the A/D converter The time it takes for 11B to perform A/D conversion,
It is equal to the time from when the A/D converter 11B performs A/D conversion until when the A/D converter 11A performs A/D conversion. Therefore, similar to the third embodiment, the problems of the conventional technology are solved.

In the above explanation, the latch circuits 2A, 2B, and 2C in FIGS. 1 and 2 are the latch circuits in FIG. The same applies to any circuit.

Furthermore, although the case where the input signal 1 and the clock signal 5 are periodic signals and the period of the input signal 1 is twice the period of the clock signal 5 has been described, the present invention is also effective in other cases. It is.

[0062]

[Effects of the Invention] As explained above, according to the present invention, the time from when the clock signal changes until the signal at the non-inverting output terminal rises, and from the time when the clock signal changes until the signal at the inverting output terminal rises. The time from when the clock signal changes until the signal at the non-inverting output terminal falls is equal to the time from when the clock signal changes until the signal at the inverting output terminal falls. A latch circuit can be obtained. Furthermore, it is extremely useful because it is possible to obtain an A/D converter that performs A/D conversion at regular intervals.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a latch circuit according to claim 1 of the present invention.

FIG. 2 is a configuration diagram of a master-slave type latch circuit according to claim 2 of the present invention.

FIG. 3 is a configuration diagram of a conventional A/D converter according to claim 3 of the present invention.

FIG. 4 is a configuration diagram of a conventional A/D converter according to claim 4 of the present invention.

FIG. 5 is a timing diagram of the latch circuit of FIG. 1 and the A/D converter of FIG. 3;

[Figure 6] Master-slave type latch circuit in Figure 2 and Figure 4
FIG. 3 is a timing diagram of the A/D converter of FIG.

FIG. 7 is a configuration diagram of a switch.

FIG. 8 is a configuration diagram of a conventional latch circuit.

FIG. 9 is a configuration diagram of a conventional master-slave type latch circuit.

FIG. 10 is a timing diagram of the latch circuit of FIG. 8;

11 is a timing diagram of the master-slave type latch circuit of FIG. 9; FIG.

[Explanation of symbols]

1 Input signal 2A First latch circuit 2B Second latch circuit 3A Non-inverting output terminal 3B Inverted output terminal 4 Inverter 5 Clock signal

Claims (4)

[Claims] 1. Consisting of first and second latch circuits that enter a transparent state or a holding state according to a clock signal, an input signal is input to an input terminal of the first latch circuit, and an inverted signal of the input signal is input to the input terminal of the first latch circuit. The clock signal is input to the input terminal of the second latch circuit, and the clock signal is input to the input terminal of the first latch circuit and the second latch circuit.
A latch circuit that is input to a clock signal input terminal of a latch circuit, wherein the output signal of the first latch circuit is a non-inverted output signal, and the output signal of the second latch circuit is an inverted output signal. 2. Consisting of first, second, and third latch circuits that enter a transparent state or a holding state in response to a clock signal, an input signal is input to an input terminal of the third latch circuit, and the third latch circuit An output signal of the circuit is input to the input terminal of the first latch circuit, an inverted signal of the output signal of the third latch circuit is input to the input terminal of the second latch circuit, and a clock signal is input to the input terminal of the first latch circuit. the clock signal input terminal of the latch circuit and the second latch circuit, the inverted signal of the clock signal is inputted to the clock signal input terminal of the third latch circuit, and the output signal of the first latch circuit is inputted to the clock signal input terminal of the third latch circuit. A master-slave type latch circuit whose output signal is an inverted output signal, and whose output signal is an inverted output signal of the second latch circuit. 3. The latch circuit according to claim 1, and first and second A/D converters, wherein the first A/D converter receives the same analog signal, and the first A/D converter receives the same analog signal. The A/D converter performs A/D conversion at a timing given by an inverted output signal, and the second A/D converter performs A/D conversion at a timing given by an inverted output signal of the latch circuit. D converter. 4. Consisting of the master-slave type latch circuit according to claim 2 and first and second A/D converters,
The first A/D converter A/D converts the same analog signal at a timing given by the non-inverted output signal of the latch circuit, and the second A/D converter converts the same analog signal into a digital signal at a timing given by the non-inverted output signal of the latch circuit. An A/D converter that performs A/D conversion at a timing given by an inverted output signal.