JPH043675B2 - - Google Patents
Info
- Publication number
- JPH043675B2 JPH043675B2 JP1528384A JP1528384A JPH043675B2 JP H043675 B2 JPH043675 B2 JP H043675B2 JP 1528384 A JP1528384 A JP 1528384A JP 1528384 A JP1528384 A JP 1528384A JP H043675 B2 JPH043675 B2 JP H043675B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring layer
- forming
- layer
- conductive wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000576 coating method Methods 0.000 claims description 23
- 239000011248 coating agent Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 20
- 239000007788 liquid Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 14
- 229920006268 silicone film Polymers 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 53
- 239000010408 film Substances 0.000 description 48
- 238000005530 etching Methods 0.000 description 17
- 239000007888 film coating Substances 0.000 description 8
- 238000009501 film coating Methods 0.000 description 8
- 239000004447 silicone coating Substances 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- -1 organosilane compound Chemical class 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 229920001296 polysiloxane Polymers 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000009499 grossing Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- SVONRAPFKPVNKG-UHFFFAOYSA-N 2-ethoxyethyl acetate Chemical compound CCOCCOC(C)=O SVONRAPFKPVNKG-UHFFFAOYSA-N 0.000 description 1
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 125000000217 alkyl group Chemical group 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000018044 dehydration Effects 0.000 description 1
- 238000006297 dehydration reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 125000001449 isopropyl group Chemical group [H]C([H])([H])C([H])(*)C([H])([H])[H] 0.000 description 1
- ZJBHFQKJEBGFNL-UHFFFAOYSA-N methylsilanetriol Chemical compound C[Si](O)(O)O ZJBHFQKJEBGFNL-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 125000001436 propyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- FCVNATXRSJMIDT-UHFFFAOYSA-N trihydroxy(phenyl)silane Chemical compound O[Si](O)(O)C1=CC=CC=C1 FCVNATXRSJMIDT-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は多層配線板の製造方法に関し、さらに
詳しくは半導体基体上に微細な導電性配線層を設
け、さらにその上に絶縁層を介して微細な導電性
配線層を積層する多層配線板の製造方法に関す
る。[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to a method for manufacturing a multilayer wiring board, and more specifically, it relates to a method for manufacturing a multilayer wiring board, and more specifically, a method for manufacturing a multilayer wiring board, in which a fine conductive wiring layer is provided on a semiconductor substrate, and an insulating layer is provided thereon. The present invention relates to a method for manufacturing a multilayer wiring board in which fine conductive wiring layers are laminated.
超LSIに代表される半導体デバイスの製造にお
いて、その集積度を高めるには導電性配線層を多
層構造とせざるを得ない。例えば半導体基板上に
アルミニウムなどを使用した第１の導電性配線層
を設け、その上にプラズマCVD・SiO2膜、スパ
ツタ・SiO2膜、プラズマCVD・Si3N4膜または低
圧（LP）CVD・PSG膜等の絶縁層を形成し、さ
らにその上に第２の配線層を形成するというふう
にして導電性配線層を幾層か設けることによつて
集積度を高めるようにしている。
In the manufacture of semiconductor devices, such as VLSIs, in order to increase the degree of integration, it is necessary to use a multilayer structure for conductive wiring layers. For example, a first conductive wiring layer using aluminum or the like is provided on a semiconductor substrate, and then a plasma CVD/SiO 2 film, a sputtering/SiO 2 film, a plasma CVD/Si 3 N 4 film, or a low pressure (LP) CVD film is formed on the semiconductor substrate. - The degree of integration is increased by forming several layers of conductive wiring layers, such as forming an insulating layer such as a PSG film, and then forming a second wiring layer thereon.
しかしながら現状は導電性配線層には導電性の
高いアルミニウムまたはその合金を使用し、写真
蝕刻法によりレリーフ状のパターンとして形成さ
れている。したがつてその上に絶縁層を上記のよ
うな方法で形成したときには導電性配線層のパタ
ーンに応じた非平滑な面となる。 However, at present, highly conductive aluminum or its alloy is used for the conductive wiring layer, and is formed as a relief pattern by photolithography. Therefore, when an insulating layer is formed thereon by the method described above, the surface becomes non-smooth in accordance with the pattern of the conductive wiring layer.
さらに第２の導電性配線層はこうして得られた
絶縁層上の一面に通常アルミニウムまたはその合
金の薄膜を真空蒸着法やスパツタリング蒸着法な
どの方法で被着させ、その上にホトレジスト層を
設け所望のマスクパターンを介して露光を行い、
現像、エツチング処理を経て形成される。 Furthermore, the second conductive wiring layer is formed by depositing a thin film of aluminum or its alloy on one surface of the insulating layer obtained in this way by a method such as vacuum evaporation or sputtering evaporation, and then forming a photoresist layer thereon as desired. Exposure is performed through a mask pattern of
It is formed through development and etching processing.
ここで上記したような絶縁層が非平滑である
と、形成した導電性配線層は絶縁層の表面状態に
応じて不均一、かつ非平滑となり、甚だしい場合
には絶縁層の突出した部分のエツジ部には導電性
材料が付着しないので断線が生じ不良品の発生の
原因ともなる。また半導体表面が非平滑であるた
めに導電性材料層などの上にホトレジスト層を設
けてマスクパターンを介して露光した際に該材料
層表面からホトレジスト活性光が乱反射してマス
クパターンに忠実な導電性配線層が得られず、微
細な配線すなわち高集積度化が期待できない。 If the insulating layer is non-smooth as described above, the formed conductive wiring layer will be uneven and non-smooth depending on the surface condition of the insulating layer, and in extreme cases, the edges of protruding parts of the insulating layer may Since no conductive material is attached to the parts, wire breakage may occur, leading to defective products. In addition, since the semiconductor surface is uneven, when a photoresist layer is provided on a conductive material layer and exposed through a mask pattern, the photoresist active light is diffusely reflected from the surface of the material layer, resulting in a conductive layer faithful to the mask pattern. Therefore, fine wiring, that is, high integration cannot be expected.
このような事情に対処する方法として非平滑な
絶縁膜上に有機膜を塗布し、表面を平坦化した後
に、有機膜および絶縁膜をドライエツチングして
平滑化する有機膜塗布方式（第30回春季応用物理
学関係連合講演会講演予稿集6a−ｏ−９
（1983））、同じく無機膜を塗布し平滑化した後に、
無機膜および絶縁膜をドライエツチングして平滑
化する無機膜塗布方式（第30回春季応用物理学関
係連合講演会講演予稿集7a−Ｐ−３（1983））、さ
らには有機膜塗布方式と無機膜塗布方式のコンビ
ネーシヨンによる平坦化方法（第44回秋季応用物
理学関係連合講演会講演予講集27a−Ｎ−10、
27a−Ｎ−11（1983））などが提案されている。
As a way to deal with this situation, the organic film coating method (No. 30) involves coating an organic film on an uneven insulating film, flattening the surface, and then dry-etching the organic film and the insulating film to smooth it. Spring Applied Physics Related Conference Lecture Proceedings 6a-o-9
(1983)), after applying and smoothing an inorganic film,
An inorganic film coating method that dry-etches and smooths inorganic films and insulating films (Proceedings of the 30th Spring Applied Physics Association Conference Proceedings 7a-P-3 (1983)), an organic film coating method and inorganic Planarization method using a combination of film coating methods (44th Autumn Applied Physics Association Lecture Preliminary Lecture Collection 27a-N-10,
27a-N-11 (1983)) have been proposed.
しかしながら有機膜塗布方式では１回の塗布に
よる平滑化性は良いが、有機膜は耐熱性が低く、
しかも絶縁層との接着強度が弱いために全体に上
部から均一にエツチング除去することができな
い。また有機膜と絶縁膜の両者に対し同一のエツ
チング速度でエツチングしなければならないの
に、有機膜と無機系絶縁膜との間の特性の相違に
よりエツチング条件の設定が難しく、また有機膜
厚の不均一性によりエツチング速度に変化が生
じ、実際のところ前記同一エツチング速度を維持
することは困難である。 However, although the organic film coating method has good smoothing properties with one coating, the organic film has low heat resistance.
Moreover, since the adhesive strength with the insulating layer is weak, it is not possible to uniformly remove the entire surface from the top. Furthermore, although both the organic film and the insulating film must be etched at the same etching speed, it is difficult to set the etching conditions due to the difference in characteristics between the organic film and the inorganic insulating film, and the thickness of the organic film is Non-uniformity causes variations in the etching rate, and in practice it is difficult to maintain the same etching rate.
さらに詳しく言えば、この場合有機膜および絶
縁膜に対し圧力、ガス、流量、半導体基板の温度
等の条件を微妙に制御してエツチング速度を調節
している。しかし実際はエツチングが進むにつれ
て、絶縁膜のエツチング速度に比して有機膜のエ
ツチング速度は速くなるというエツチング速度の
不均一化現象が起きる。結果として最初の絶縁膜
表面形状に対して平滑化されても依然として絶縁
膜の凹凸形状が残留することになるという欠点が
ある。 More specifically, in this case, the etching rate is adjusted by delicately controlling conditions such as pressure, gas, flow rate, and temperature of the semiconductor substrate for the organic film and the insulating film. However, in reality, as etching progresses, a phenomenon occurs in which the etching rate becomes non-uniform, such that the etching rate of the organic film becomes faster than the etching rate of the insulating film. As a result, even if the initial surface shape of the insulating film is smoothed, the uneven shape of the insulating film still remains.
また無機膜塗布方式では上記のようなエツチン
グの際の不都合は生じにくいが、１回塗布で厚膜
を形成することが困難であり、非平滑化面の凹部
を埋めるためには多重塗布を行わなければなら
ず、またパターン幅の影響を受けやすく密なパタ
ーンでは厚く、粗なパターンでは薄く塗布される
特性を有し、半導体基板表面全体として均一な平
坦面が得られにくい。 In addition, with inorganic film coating methods, the above-mentioned problems during etching are less likely to occur, but it is difficult to form a thick film with one coat, and multiple coats are required to fill in the recesses on an uneven surface. Moreover, it is easily influenced by the pattern width, and has the characteristic that it is coated thickly for dense patterns and thinly for rough patterns, making it difficult to obtain a uniform and flat surface over the entire surface of the semiconductor substrate.
さらに両者の欠点を補うべく提案された有機膜
塗布方式と無機膜塗布方式のコンビネーシヨンに
よる平坦化方法では一層目の無機膜が厚膜化して
クラツクが入りやすく、また２度のエツチング工
程あるいは２度の焼成工程が必要となり、手間が
かかるという欠点がある。 Furthermore, in the planarization method using a combination of an organic film coating method and an inorganic film coating method, which has been proposed to compensate for the drawbacks of both methods, the first layer of inorganic film becomes thick and cracks are likely to occur. The drawback is that it requires multiple firing steps, which is time-consuming.
本発明は上記した従来の欠点を解消することを
目的としてなされたものである。すなわち本発明
は半導体デバイスにおける多層配線構造をもつた
微細な導電性配線層を形成し、しかも層間絶縁膜
に信頼性の高い多層配線板の製造方法を提供する
ものである。
The present invention has been made for the purpose of solving the above-mentioned conventional drawbacks. That is, the present invention provides a method for manufacturing a multilayer wiring board in which a fine conductive wiring layer having a multilayer wiring structure in a semiconductor device is formed and the interlayer insulating film is highly reliable.
本発明者らは非平滑な絶縁層上に第１の有機シ
リコーン系被膜を形成し、さらにその上に第１の
有機シリコーン系被膜よりも有機成分含有量の多
い第２の有機シリコーン系被膜を形成することに
より従来技術の欠点が解消され得ることを見出
し、その知見に基いて本発明を完成した。
The present inventors formed a first organosilicone film on a non-smooth insulating layer, and further formed a second organosilicone film having a higher organic component content than the first organosilicone film. It was discovered that the drawbacks of the prior art could be overcome by forming a wafer, and the present invention was completed based on this knowledge.
すなわち本発明は半導体基板上に第１の導電性
配線層を設け、該基体上全面に厚さが該導電性配
線層よりも厚い絶縁層を被覆し、その上に第１の
有機シリコーン系被膜形成用塗布液を被着し、そ
れにより絶縁膜表面を平滑化した後、さらにその
上に第１の有機シリコーン系被膜よりも有機成分
含有量の多い第２の有機シリコーン系被膜形成用
塗布液を被着し、それによつてほぼ平坦な表面を
形成した後、上部から上記導電性配線層が裸出し
ない程度に蝕刻してその上に第２の導電性配線層
を設け、さらに必要ならば以下同様にして多層化
することを特徴とする多層配線板の製造方法を提
供するものである。 That is, the present invention provides a first conductive wiring layer on a semiconductor substrate, covers the entire surface of the substrate with an insulating layer that is thicker than the conductive wiring layer, and coats the entire surface of the substrate with a first organic silicone coating. After applying the forming coating liquid and smoothing the surface of the insulating film, a second organic silicone film forming coating liquid having a higher organic component content than the first organic silicone film is applied thereon. After forming a substantially flat surface, the conductive wiring layer is etched from above to such an extent that the conductive wiring layer is not exposed, and a second conductive wiring layer is formed thereon. Hereinafter, a method for manufacturing a multilayer wiring board characterized by forming multiple layers in the same manner is provided.
〔詳細な説明〕
まず半導体基板上に常法により、アルミニウ
ム、白金シリサイド、タングステン等の導電性材
料による配線が形成され、その上に絶縁層として
例えばリンケイ酸ガラス（PSG）、ホウケイ酸ガ
ラス（BSG）あるいはシリコン窒化物等をCVD
法あるいはプラズマCVD法等により形成する。
このとき前記導電性配線層の厚みよりも絶縁層の
方を多少厚くすることが好ましい。得られた絶縁
層の形状は半導体基板上に導電性配線層が形成さ
れて得られた凹凸の形状に類似している。この凹
凸の形状における凹部に本発明の特徴とするケイ
素含有量の多い第１の有機シリコーン系被膜形成
用塗布液を用いて塗布し、凹部を埋めて平滑化を
行う。[Detailed Description] First, wiring made of a conductive material such as aluminum, platinum silicide, or tungsten is formed on a semiconductor substrate by a conventional method, and then an insulating layer made of, for example, phosphosilicate glass (PSG) or borosilicate glass (BSG) is formed on the semiconductor substrate. ) or CVD of silicon nitride, etc.
It is formed by a plasma CVD method or the like.
At this time, it is preferable that the insulating layer is somewhat thicker than the conductive wiring layer. The shape of the obtained insulating layer is similar to the shape of unevenness obtained by forming a conductive wiring layer on a semiconductor substrate. The first coating liquid for forming an organic silicone film having a high silicon content, which is a feature of the present invention, is applied to the concave portions of this uneven shape, and the concave portions are filled and smoothed.
本発明における第１層に用いることのできる有
機シリコーン系被膜形成用塗布液としては下記の
アルコキシシラン化合物
（RO）oSi（OH）4-o
（Ｒはメチル基、エチル基、プロピル基、イソ
プロピル基、ｎ−ブチル基、ｔ−ブチル基な
どの比較的低級のアルキル基、oは４以下の正
の整数）
または下記のオルガノシラン化合物
RoSi（OH）4-o
Ｒおよびoは前掲のものと同じ）
および上記アルコキシシラン化合物と上記オルガ
ノシラン化合物のオリゴマーまたはポリマーなど
がある。上記各式中のＲは炭素数が小さいものが
好ましく、またｎは１または２であることが好ま
しい。 The coating liquid for forming an organic silicone film that can be used for the first layer in the present invention is the following alkoxysilane compound (RO) o Si(OH) 4-o (R is a methyl group, an ethyl group, a propyl group, an isopropyl group). ( O is a positive integer of 4 or less) or the following organosilane compound R o Si (OH) 4-o R and o are the above-mentioned (same as above) and oligomers or polymers of the above alkoxysilane compounds and the above organosilane compounds. In each of the above formulas, R preferably has a small number of carbon atoms, and n is preferably 1 or 2.
これまでの無機被膜形成用塗布液（Si（OH）4）
では実用上平坦面に塗布した場合の膜厚は3000〜
4000Åが限度であつたが、上記本発明の塗布液は
6000〜7000Åの被膜を形成し、またパターン幅が
3μm程度の凹凸がある基板表面での凹部をほぼ埋
める厚膜が形成される。 Conventional coating liquid for inorganic film formation (Si(OH) 4 )
In practical terms, the film thickness when applied to a flat surface is 3000 ~
The coating liquid of the present invention described above had a maximum thickness of 4000Å.
Forms a film with a thickness of 6000 to 7000Å, and the pattern width is
A thick film is formed that almost fills the depressions on the substrate surface, which has irregularities of about 3 μm.
さらに上記第１の有機シリコーン系被膜上に第
１の有機シリコーン系被膜よりも有機成分含有量
の多い第２の有機シリコーン系被膜形成用塗布液
を用いて塗布する。第２層に用いることのできる
有機シリコーン系被膜形成用塗布液としては前記
したものの中で第１層に用いたものよりも有機成
分含有量の多いものが使用できるが、特に下記オ
ルガノシラン化合物
R′oSi（OH）4-o
（R′はフエニル基、ビニル基など、oは４以下の
正の整数）
および上記オルガノシラン化合物の脱水縮合した
オリゴマーおよびポリマーなどである。また上記
式中のR′がメチル基などのアルキル基であるオ
ルガノシラン化合物との混合物も使用される。上
記有機シリコーン系被膜形成用塗布液は膜厚3μm
以上の被膜を形成するのに特に有効である。 Further, a coating liquid for forming a second organic silicone film having a higher organic component content than the first organic silicone film is applied onto the first organic silicone film. As the coating liquid for forming an organic silicone film that can be used for the second layer, among the above-mentioned ones, those having a higher organic component content than those used for the first layer can be used, but in particular, the following organosilane compound R ' o Si(OH) 4-o (R' is a phenyl group, a vinyl group, etc., and o is a positive integer of 4 or less) and oligomers and polymers obtained by dehydration condensation of the above organosilane compounds. A mixture with an organosilane compound in which R' in the above formula is an alkyl group such as a methyl group may also be used. The coating liquid for forming the organic silicone film mentioned above has a film thickness of 3 μm.
It is particularly effective for forming the above coatings.
第１の有機シリコーン系被膜には前述のエツチ
ング速度の不均一化現象をおさえるために、元来
絶縁層とエツチング速度の等しいもの、すなわち
SiO2成分が多いものが好ましい。これに該当す
るものとして、OCD Type6（東京応化工業(株)製）
が実用的である。 In order to suppress the above-mentioned non-uniformity of etching rate, the first organic silicone coating is originally made of a material having an etching rate equal to that of the insulating layer, i.e.
It is preferable to use a material containing a large amount of SiO 2 component. OCD Type 6 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) falls under this category.
is practical.
第２の有機シリコーン系被膜には第１の有機シ
リコーン系被膜によつて解消しきれなかつた段差
を埋めるために充分な厚膜を形成できる塗布液が
好ましい。このようなものとしてOCD Type7
（東京応化工業(株)製）が実用的である。 The second organic silicone coating is preferably a coating liquid that can form a thick enough film to fill in the steps that cannot be completely eliminated by the first organic silicone coating. OCD Type7 as something like this
(manufactured by Tokyo Ohka Kogyo Co., Ltd.) is practical.
上記第１層および第２層の有機シリコーン系被
膜形成用塗布液は通常有機溶媒に溶解された塗布
液として用いられる。これらの塗布液はスピンナ
ーにより基体表面に塗布するのが好ましい。 The coating liquid for forming the organic silicone coating for the first layer and the second layer is usually used as a coating liquid dissolved in an organic solvent. These coating liquids are preferably applied to the substrate surface using a spinner.
次に第２および第１の有機シリコーン系被膜と
絶縁層を通常の方法、例えば乾式のプラズマある
いはRIEまたは湿式のエツチング液に浸漬する方
法により上部から導電性配線層が裸出しない程度
に蝕刻する。 Next, the second and first organic silicone films and the insulating layer are etched by a conventional method, such as dry plasma, RIE, or wet etching to an extent that the conductive wiring layer is not exposed from above. .
また導電性配線層が裸出した場合には絶縁層を
その上に改めて設ければ本発明の目的を達成でき
る。 Further, when the conductive wiring layer is exposed, the object of the present invention can be achieved by newly providing an insulating layer thereon.
このようにして得られた平坦化された絶縁層上
に導電性材料の被膜を形成し、ホトリソグラフイ
法により所望のパターンを形成して第２の導電性
配線層を設けるように順次処理することによつて
多層配線板を得ることができる。 A film of a conductive material is formed on the flattened insulating layer thus obtained, and a desired pattern is formed by photolithography to provide a second conductive wiring layer. By this, a multilayer wiring board can be obtained.
本発明によれば半導体デバイスの製造工程で生
ずる段差を有効に解消することができる。例えば
ケイ素含有量の多い有機シリコーン系被膜形成用
塗布液を塗布し、さらに有機成分含有量の多い有
機シリコーン系被膜形成用塗布液を塗布すること
により、被膜表面は平坦となり、エツチングによ
り該表面の平坦性を維持したまま、絶縁膜を平坦
化することができる。このことにより多層配線層
の断線を防止し、層間配線の信頼性を向上させる
ことができる。
According to the present invention, it is possible to effectively eliminate steps that occur during the manufacturing process of semiconductor devices. For example, by applying an organic silicone film-forming coating liquid with a high silicon content and then further applying an organic silicone film-forming coating liquid with a high organic component content, the surface of the film becomes flat, and the surface is smoothed by etching. The insulating film can be planarized while maintaining flatness. This can prevent disconnection of the multilayer wiring layer and improve the reliability of the interlayer wiring.
次に本発明の実施例を示す。 Next, examples of the present invention will be shown.
実施例 １
酸化被膜を有するシリコンウエハ上にアルミニ
ウムを蒸着法によつて1.0μmの厚みに被着し、写
真蝕刻法により所望の配線パターンを形成する。
この基板の上にCVD、PSG膜を約1.5μmの厚み
となるように形成し、ジエトキシジヒドロキシシ
ランの10重量％エタノール溶液からなる第１の有
機シリコーン系被膜形成用塗布液（OCD Type6
Si−10000、東京応化工業(株)製）を3000rpmでス
ピンコートし、300℃で30分間乾燥した。このと
き膜厚は3μmのパターン幅の凹部中央で0.5μmで
あつた。Example 1 Aluminum was deposited to a thickness of 1.0 μm on a silicon wafer having an oxide film by vapor deposition, and a desired wiring pattern was formed by photolithography.
A CVD and PSG film was formed on this substrate to a thickness of approximately 1.5 μm, and a first organic silicone film-forming coating solution (OCD Type 6
Si-10000 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was spin coated at 3000 rpm and dried at 300°C for 30 minutes. At this time, the film thickness was 0.5 μm at the center of the recess with a pattern width of 3 μm.
次にポリフエニルシリコーンラダーポリマー
（（−C6H5SiO3/2）＝）の30重量％エチレングリコー
ルモノエチルエーテルアセテート溶液からなる第
２の有機シリコーン系被膜形成用塗布液（OCD
Type7 32R−30000、東京応化工業(株)製）を
4000rpmで20秒間スピンコートし、400℃でベー
キングを行つた。このときの第２の有機シリコー
ン系被膜の膜厚は平坦部で1.0μmであつた。 Next , a second organic silicone film -forming coating solution ( OCD
Type7 32R−30000, manufactured by Tokyo Ohka Kogyo Co., Ltd.)
Spin coating was performed at 4000 rpm for 20 seconds, and baking was performed at 400°C. The thickness of the second organic silicone coating at this time was 1.0 μm at the flat portion.
次いで85容量％濃度のCF4と15容量％濃度のO2
とからなる混合ガスを用いてOAPM−400（東京
応化工業(株)製プラズマ処理装置）によりRIEモー
ドで12分間エツチングを行つた。その結果、エツ
チング深度は1.0μmでその表面は極めて平坦であ
つた。その後常法により第２の導電性配線層を設
けることにより２層の多層配線が得られた。 Then 85% concentration by volume of CF4 and 15% concentration by volume of O2
Etching was performed for 12 minutes in RIE mode using OAPM-400 (plasma processing apparatus manufactured by Tokyo Ohka Kogyo Co., Ltd.) using a mixed gas consisting of: As a result, the etching depth was 1.0 μm and the surface was extremely flat. Thereafter, a second conductive wiring layer was provided by a conventional method to obtain a two-layer multilayer wiring.
実施例 ２
実施例１と同様に処理されて形成された凹凸形
状を有するPSG膜上にメチルトリヒドロキシシ
ラン（CH3Si（OH）3）の10重量％とエチルシリケ
ートの６量体オリゴマー２重量％のエタノール溶
液を3000rpmでスピンコートし、200℃で60分間
乾燥し、0.4μmの膜厚を得、次にフエニルトリヒ
ドロキシシラン（C6H5Si（OH）3）の30重量％エ
チレングリコールモノエチルエーテルアセテート
溶液を4000rpmでスピンコートし、400℃でベー
キングし1.2μmの膜厚を得て、ほとんど平坦な表
面を得た。Example 2 10% by weight of methyltrihydroxysilane (CH 3 Si(OH) 3 ) and 2 weights of hexamer oligomer of ethyl silicate were applied on a PSG film having an uneven shape formed by the same treatment as in Example 1. % ethanol solution at 3000 rpm and dried at 200 °C for 60 min to obtain a film thickness of 0.4 μm , then 30 wt% ethylene of phenyltrihydroxysilane ( C6H5Si (OH) 3 ) A glycol monoethyl ether acetate solution was spin-coated at 4000 rpm and baked at 400°C to obtain a film thickness of 1.2 μm and an almost flat surface.
次に実施例１と同様にエツチングしたところ絶
縁膜はほぼ平坦となつた。 Next, when etching was performed in the same manner as in Example 1, the insulating film became almost flat.
Claims (1)
該基体上全面に厚さが該配線層よりも厚い絶縁層
を被覆し、その上に第１の有機シリコーン系被膜
形成用塗布液を被着し、さらにその上に第１の有
機シリコーン系被膜よりも有機成分含有量の多い
第２の有機シリコーン系被膜形成用塗布液を被着
し、それによつてほぼ平坦な表面を形成した後、
上部から上記導電性配線層が裸出しない程度に蝕
刻してその上に第２の導電性配線層を設け、さら
に必要ならば以下同様にして多層化することを特
徴とする多層配線板の製造方法。1. Providing a first conductive wiring layer on a semiconductor substrate,
An insulating layer having a thickness thicker than the wiring layer is coated on the entire surface of the substrate, a coating liquid for forming a first organic silicone film is applied thereon, and a first organic silicone film is further applied thereon. After applying a second organosilicone film-forming coating liquid having a higher organic component content than that of the second organosilicone coating, thereby forming a substantially flat surface,
Production of a multilayer wiring board, characterized in that the conductive wiring layer is etched from above to such an extent that the conductive wiring layer is not exposed, a second conductive wiring layer is provided thereon, and if necessary, multilayering is performed in the same manner. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1528384A JPS60161697A (en) | 1984-02-01 | 1984-02-01 | Method of producing multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1528384A JPS60161697A (en) | 1984-02-01 | 1984-02-01 | Method of producing multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60161697A JPS60161697A (en) | 1985-08-23 |
| JPH043675B2 true JPH043675B2 (en) | 1992-01-23 |
Family
ID=11884525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1528384A Granted JPS60161697A (en) | 1984-02-01 | 1984-02-01 | Method of producing multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60161697A (en) |
-
1984
- 1984-02-01 JP JP1528384A patent/JPS60161697A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60161697A (en) | 1985-08-23 |
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