JPH0442028B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a tennis counter that counts tennis scores, and in particular, it automatically enters a tie-break mode during a tie-break, and the display during a tie-break is also improved. I tried to make it easier to see.

(Prior art) Traditionally used as a tennis counter in Japanese Patent Application Laid-Open No. 1983-
No. 129283 or JP-A-58-13066 are disclosed. These tennis counters display all data regarding tennis scores by operating a switch. In particular, when the number of games obtained by the opponents becomes 6 vs. 6, the point counting method can be changed from the conventional 15, 30,
Instead of 40, count as 1, 2, 3, and when one of the opponents obtains 7 or more points and has a 2 or more point difference over the opponent, the set is established.
So-called tie-breaks can now be counted.

(Problems to be solved by the invention) However, in the past, when there was a tie-break, the user had to operate a switch;
In addition, because the tie-break points are displayed in the same way as usual, there are many inconveniences, such as it is difficult to tell whether the game has entered a tie-break or not.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a tennis counter that is easier to use during a tie-break.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a counter that counts tie-break points on a point display section that displays points when the number of games obtained is 6 to 6. In addition, the display method is that the point display is a digital display of 2 digits each, but it is displayed with 1 digit each, and if one opponent has obtained 7 or more points and The present invention is characterized in that the set is established by detecting that the player has a difference of 2 points or more with respect to the other opponent, and the next set is started.

(Embodiment) FIG. 1 is a block diagram showing the circuit configuration of a tennis counter watch according to an embodiment of the present invention, and FIG. 2 is a diagram showing the segment arrangement of the display section shown in FIG. 1.
FIGS. 3 to 9 are diagrams showing the display state.

As shown in FIG. 2, the display section 2 includes a time display section 4 consisting of sun-shaped segments 4a and 4b and also serving as a point display section, and a time display section 4 consisting of sun-shaped segments 6a and 4b.
6b, a minute display section 6 which also serves as a point display section, and small Japanese-shaped segments 8a, 8.
a seconds display section 8 consisting of b and also serving as a game display section;
Segments 10a, 10b, 10c, 10 corresponding to the letters of the day of the week formed by printing etc.
A day of the week display section 10 consisting of d, 10e, 10f, and 10g and also serving as a set display section is provided.

The display section 2 shown in FIG. 3 is in a time display state, and displays Tuesday at 12:30:45.

The display section 2 shown in FIG. 4 is in a tennis score display state, with the hour display section 4 and the minute display section 6 displaying the points of each opponent, and the second display section 8 having a day-shaped segment 8a, 8b displays the game points of each opponent, and the day of the week display section 1
0 displays the set count of each opponent starting from segment 10d.

In this example, as shown in FIG.
When it becomes a duel, the point display (hour digit display section 4) of the opponent who gained the advantage
The display is set to blink to notify you of this.

In addition, if a court change is required, for example, when the fifth game ends in the state shown in FIG. 6, the game count displayed on the seconds display section 8 and the day of the week as shown in FIG. Display section 10
It is also set to display the set count displayed in the left and right directions.

Furthermore, in this embodiment, when the game count becomes 6 to 6 as shown in FIG. The score is set to be displayed only on the glyph segment 6a, and when the score is displayed as shown in Figure 9 with a difference of 2 points or more between 7 points or more, the score will be displayed even after one set is completed. It is set to return to the display state of .

Next, the circuit configuration and detailed circuit configuration of each circuit will be explained based on FIG.

The oscillator 10 is composed of a crystal oscillator or the like, and outputs a reference signal. The frequency divider 12 divides the frequency of the reference signal and outputs a timing signal consisting of one pulse per second. The second digit counter 14 includes a second counter 16 that counts this time signal and outputs a second signal S, and a second counter 16 that counts the output signal of the second counter 16 and outputs a 10 second signal.
It consists of a 10 second counter 18 that outputs _S10 . The minute digit counter 20 is connected to the second digit counter 14.
The minute counter 22 counts the output signals of the minute counter 22 and outputs the minute signal M, and the 10 minute counter 24 counts the output signals of the minute counter 22 and outputs _{the 10} minute signal M10. Hour digit counter 2
6 is an hour counter 28 that counts the output signal of the minute digit counter 20 and outputs the hour signal H, and an hour counter 28 that counts the output signal of the counter 28 and outputs the 10 o'clock signal.
It consists of a 10 o'clock counter 30 that outputs _H10 . The day of the week counter 32 is the hour digit counter 26
It counts the output signals of and outputs day of the week signals _D1 to _D7 .

Point input switches 34 and 36 are for inputting the points of each opponent, and apply signals A and B to point counters 100 and 200 via chatter prevention circuits 38 and 40, respectively. This point counter 100,200
becomes movable when the output Q of the flip-flop 46 becomes H level via the chattering prevention circuit 44 by operating the changeover switch 42, and counts points according to the operation of the point input switches 34 and 36.

The signals N _A , N _A10 , N _B , N _B10 indicating the count contents of the point counters 100 and 200 are the output signals of the hour digit counter 26 and the minute digit counter 20.
H ₁₀ , H, M ₁₀ , M together with hour digit selection circuit 1100
and are applied to the minute digit selection circuit 1200, respectively.
At this time, the hour digit selection circuit 1100 and the minute digit selection circuit 120
0 is the signal H ₁₀ , H, M ₁₀ , M and the signal N _A , N _A10 ,
_NB and _NB10 are switched and output, and the time or point is displayed on the hour display section 4 and minute display section 6 of the display section 2 via the driver 1400.

If one of the opponents accumulates points and raises game points, the point counter will be 100 or 20.
A signal X _A or X _B is output from 0. The game number counters 300 and 400 count the signals X _A and X _B to count the game points of each opponent, and output signals G _A and G _B indicating the contents.
These signals G _A and G _B are applied to the seconds digit selection circuit 1300 together with the output signals S and S ₁₀ of the seconds digit counter 14 .

This second digit selection circuit 1300 switches and outputs the signals S, _S10 and the signals G _A and G _B , and the driver 1400
Seconds or game points are displayed on the seconds display section 8 of the display section 2 via the display section 2.

As the match progresses, if one of the opponents wins six games first and gains a set point by two or more games, the game number counter 300 or 400 outputs a signal x ₉ or x ₁₀ , indicating the set number. Counters 500 and 600 count these signals x ₉ and x ₁₀ and output signals T _A1 , T A2 , and _TA2 indicating set counts.
Output T _A3 , T _B1 , T _B2 , and T _B3 . This signal T _A1
-T _A3 , T _B1 -T _B3 are applied to the day of the week selection circuit 1500 together with the output signals D ₁ -D ₇ of the day of the week counter 32. This day selection circuit 1500 receives signals D ₁ to
D ₇ and the signals T _A1 to T _A3 and T _B1 to T _B3 are switched and output, and the day of the week display section 1 of the display section 2 is displayed via the driver 1600.
Displays the day of the week or set count at 0.

The advantage display circuit 700 outputs the output signals N _A , N A10 , N _A10 of the point counters 100, 200,
When N _B and N _B10 are input and the count value reaches a 40-40 duel, this is detected and a signal C _A or C _B is output indicating that one of the opponents has an advantage if he or she raises a point. do. This signal C _A ,
C _B is applied to the driver 1400, and the point displayed on the hour display section 4 or minute display section 6 of the display section 2 is made to blink, indicating that the opponent corresponding to the blinking display has an advantage. It shows. Moreover, this advantage display circuit 70
0 outputs a signal P _A or P _B when it detects that one of the opponents has won two points in a row during dual use, and applies this signal P _A or P _B to the point counter 100 or 200. The signal P _A or P _B applied to the point counter 100 or 200 is
Output signal of point counter 100 or 200
Occurs on X _A or X _B , game number counter 300
Or 400 is applied and added as game points.

The tie-break display circuit 800 receives the signals G _A6 and G _B6 output from the game number counters 300 and 400 and determines whether or not it is a tie-break.
In other words, the game points for signals G _A6 and G _B6 are "6"
This signal indicates that G _A6 ,
When both G _{and B6} are output, the game count of the opponents becomes 6 to 6, indicating a tie-break. Therefore, the tie-break display circuit 800 is
It detects whether or not both signals G _A6 and G _B6 are output to determine whether it is a tie-break or not, and when it becomes a tie-break, the output signal F selects the time digit to indicate that it is in a tie-break. circuit 1100
are instructed to the minute digit selection circuit 1200, and these are the eighth
As shown in the figure, the sun-shaped segments 4b, 6
Switch to the tie-break only display by lighting only a. In addition, this tie-break display circuit 800
counts the points obtained during the tie-break in place of the point counters 100 and 200, outputs the count values as signals E _A and E _B , and applies them to the hour digit selection circuit 1100 and the minute digit selection circuit 1200. As a result, the hour digit selection circuit 1100 and the minute digit selection circuit 1200 display the tie-break point on the day-shaped segments 4b and 6a of the display section 2 via the driver 1400. During this tie-break, when one opponent's points are 7 points or more and there is a difference of 2 points or more, the tie-break display circuit 800 sends a signal U _A indicating that one opponent has obtained this set point. Or output U _B. This signal U _A or U _B is applied to the game number counter 300 or 400, and is generated in their output signal x ₉ or x ₁₀ to increment the count of the set number counter 500 or 600 by one.

The display inversion circuit 900 receives signals X _A , X _B indicating the end of each game, and U _A , indicating the end of the tie-break.
It inputs U _B and a signal J ₁ indicating a court change during a tie-break, and outputs a signal J that inverts the display based on each signal. This signal J is transmitted to the hour digit selection circuit 1100 and the minute digit selection circuit 12.
00, second digit selection circuit 1300, day of the week digit selection circuit 1
500, and as a result, during a normal court change, the game count displayed on the second display section 8 of the display section 2 and the set count displayed on the day of the week display section 10 are swapped left and right, and also during tie-making. At the time of a court change in the middle, in addition to reversing these displays, the tie-break points displayed in the sun-shaped segments 4b and 6a are also displayed with the left and right reversed.

In addition, point counters 100 and 200, game number counters 300 and 400, and set volume counter 5
00,600 is the point input switch 34,3
6 simultaneously, the reset circuit 10
It is reset by the Clear signal output from 00.

Figure 10 shows the above point counters 100, 20.
0 and a circuit configuration of a display inversion circuit 900, and FIGS. 11 and 12 are time charts thereof.

The point counters 100 and 200 are provided with AND gates 102 and 202 that input point input signals A and B, a switching signal Q, and signals R and F indicating whether or not it is a de-use or a tie-break. , 202 output signals r ₁ , r ₂
Quaternary counter 104,2 that inputs and counts
04, a decoder 106, 206 that converts the count value of the counter 104, 204 into a code signal of 00, 15, 30, 40, and a counter 104, 204.
cut-up signals r ₃ and r ₄ and a signal P _A indicating the end of deuse from the advantage display circuit 700,
OR gates 108 and 208 are provided for inputting P _B and outputting game end signals X _A and X _B , respectively, and a point counter 200 is provided with a signal
An OR gate 210 is also provided for inputting X _A , X _B and a Clear signal from the reset circuit 1000 to reset the counters 104 and 204 .

The display inversion circuit 900 includes an OR gate 902 that receives signals X _A and X _B indicating that one game has ended and signals U _A and U _B that indicates that a tie break has ended, and an output signal r of the OR gate 902. Flip-flop 90 which inputs ₅ to clock input φ
4, and a flip-flop 906 that inputs the output _r7 of the flip-flop 904 to the clock input φ.
an AND gate 908 which is normally open and inputs the output signal _J0 of flip-flop 906, and an AND gate 910 which is open during a tie-break.
an OR gate 912 that inputs the outputs of the AND gates 908 and 910 and outputs an inverted signal J;
An OR gate 914 is provided which inputs the Clear signal and the set end signal _X13 to reset the flip-flop 904.

First, the point input switches 34 and 36 are operated simultaneously to output a Clear signal from the reset circuit 1000 consisting of an AND gate, and the point counters 100 and 200 and the display inversion circuit 900 are output.
Reset. Thereafter, when the point input switches 34 and 36 are operated, pulses are generated in the signals A and B, respectively, and the output signals of the AND gates 102 and 202, which are normally open, are generated and the counter 1 is output.
04,204. This counter 10
The count content of 4,204 is the decoder 106,2.
Hour digit and minute digit selection circuit 1100, 12 by 06
00, and when one opponent wins 4 points and 4 pulses are generated on the signal _r1 or _r2 , the counter 104 or 204 outputs the output signal.
Generate a pulse to r ₃ or r ₄ , or gate 108
Alternatively, signals X _A and X _B are generated via 208 to inform the display inverting circuit 900 that the game has ended.

When a pulse is generated in the output signal r ₅ of the OR gate 902 of the display inversion circuit 900, the first pulse indicates that the first game has ended, and this pulse causes the output signal r ₆ of the flip-flop 904 to go to the L level. The output Q of the flip-flop 906 of the stage is set to H level. This flip-flop 90
When the output signal _J0 of 6 becomes H level, the output of AND gate 908, which is normally open, also becomes H level, and the inverted signal J output from OR gate 912 becomes H level.
The signal J rises to level and instructs to invert the display by changing the state of this signal J. When the next second game ends and a pulse is generated in the signal _r5 , this pulse is also applied to the clock input φ of the flip-flop 904, so the output signal _r6 becomes H level, but the output signal _r6 is not applied. flipflop 9
The output of 06 does not change and the inverted signal J also maintains the H level state.

Thereafter, when the odd-numbered game ends, the inversion signal J changes its state to H level or L level, and the display is inverted each time.

When a set ends with an even numbered game,
For example, as shown in FIG. 1, when the game count is 6 to 2 and the eighth game ends, the set end signal X ₁₃ is output from the game number counter 400.
A pulse is generated. This pulse is OR gate 9
14 output signal _r7 and flip-flop 9
Only 04 is reset. Therefore, in the next set, the first game is started with the inversion signal J at the L level, and the inversion signal J is inverted at the end of the odd-numbered game.

On the other hand, one set is an odd numbered game, for example, the first
As shown in FIG. 2, when the game count ends at 6 to 3, a pulse is generated in the set end signal _X13 of the game number counter 400, so that the flip-flop 904 is reset. Therefore, even in this case, in the next set, the inverted signal J is H.
The first game is started from the level state, and the inversion signal J is inverted at the end of the odd-numbered game.

In this way, the display inversion circuit 900 is configured such that regardless of whether one set ends with an even or odd numbered game, the inversion signal J is inverted at the end of the first game of the next set. You can display court changes as the game progresses.

At the time of deuse, as shown in Figure 12,
Signal R from advantage display circuit 700 is L
To reach the level, point counter 100,2
No pulses of signals A and B are generated at the outputs of AND gates 102 and 202 in 00, and one of the opponents
When a point is obtained first, a pulse is generated in the output signal P _A or P _B of the advantage display circuit 700.
For example, if a pulse occurs in signal P _A , this pulse is generated in signal X _A via OR gate 108 of point counter 100, which in turn generates a pulse in output signal r ₅ of OR gate 902. The pulse generated in this signal _r5 causes the display inversion circuit 900 to operate in the same manner as described above.

During a tie-break, the signal F from the tie-break display circuit 800 goes to L level, so the point counter 100,
200 is not activated (this signal F is the signal U _A or U _B
(This will be explained later), when one of the opponents has a difference of 2 points or more with 7 points or more, the output signal U _A or U _B of the tie-break display circuit 800 A pulse is generated. For example, if a pulse is generated in the signal U _B , this pulse is generated in the output signal _r5 of the OR gate 902 of the display inverting circuit 900, and the display inverting circuit 900 works.

Note that the coat change performed during the tie-break is performed when the signal _J1 output from the tie-break display circuit 800, which will be described later, becomes H level, and the inverted signal J is output via the AND gate 914 and the OR gate 916, which are open during the tie-break. This occurs and the display is reversed.

FIG. 13 shows the game number counter 30 shown in FIG.
0,400 and the circuit configuration of the set number counters 500, 600, and FIGS. 14 to 16 are time charts thereof.

AND gates 302 and 4 input the output signals X _A and X _B of the point counters 100 and 200 into one input terminal of the game number counters 300 and 400, respectively, and invert the inverted signal J and input it to the other input terminal.
02, AND gates 304 and 404 which each input the signals X _B and X _A to one input terminal and input the inverted signal J to the other input terminal, and these AND gates 3
OR gates 306 and 406 that input the outputs of 02, 304, 402, and 404, and this OR gate 3
06,406 output signals x ₁ and x ₂ are clock input φ
and a decoder 31 that converts the count values of these counters 308 and 408 into code signals of "0 to 6".
0,410, and a signal G _A5 indicating the respective count values "5" and "6" of the decoders 310 and 410,
Noah gate 412,3 inputting G _A6 , G _B5 , G _B6
12 and signals G _A6 and G _B6 indicating the count value "6" of the decoders 310 and 410, respectively, are inputted to one input terminal, and the output signals of the NOR gates 312 and 412 are input.
AND gate 31 that inputs x ₃ and x ₄ to other input terminals
4,414, the signals U _A and U _B from the tie-break display circuit 800, the output signals x ₅ and x ₆ of the AND gates 314 and 414, and the count-up signals x ₇ and x ₈ of the counters 308 and 408. , set point signals x ₉ , x ₁₀
16 are provided, and a game number counter 4 is provided.
00 is an OR gate 4 which inputs the signals x ₉ , x ₁₀ and the Clear signal to reset the counters 308 and 408.
18 are also provided.

The set number counters 500, 600 are outputted from the game number counters 300, 400. Quaternary counters 502, 602 that input and count set point signals x ₉ , x ₁₀ , and decoders 504, 604 that convert the count values of these counters 502, 602 into code signals are provided.
In addition, the set number counter 600 has a counter 50.
2,602 count up signals x ₁₁ , x ₁₂ and
An OR gate 606 is also provided for inputting a Clear signal to reset the counters 502, 602.

Basically, the game number counters 300 and 400 count the pulses generated in the point signals X _A and X _B output from the point counters 100 and 200 using counters 308 and 408, respectively, and the decoders 310 and 410 use these count values. Signal G _A , G _B
is applied to the second digit selection circuit 1300 to display the display section 2.
The game count is displayed on the second display section 8. The signals X _A and X _B applied to the game number counters 300 and 400 are inverted signals J that switch from L to H or from H to L at the time of court change.
AND gates 302, 304, 40 that input
2,404 determines which game number counter 300,400 is supplied.

For example _, as shown in FIG. 14, when one of the contestants raises the game point and a pulse is generated in the signal AND gate 302 and OR gate 306 in the state
Generates a signal via _x1 . After that, as mentioned above, the inverted signal J switches to H level, and the AND gates 304 and 404 replace the AND gates 302 and 402.
becomes open. Therefore, if the other opponent raises a game point and there is a pulse again on _signal Since the input switch 34 now corresponds to the other player, when this switch 34 is operated and a pulse is generated in the signal X _A , this game point becomes the point of the other player), and this pulse is A signal x ₂ is generated via an AND gate 404 and an OR gate 406.

In this way, a pulse is generated in the signal x ₁ or x ₂ ,
For example, as shown in FIG. 14, when the counter 308 counts "6", the output signal G _A6 of the decoder 310 becomes H level, and if the counter 408 does not count "5" or "6" at this time, The output signal _x5 of the AND gate 314 in the open state also becomes H level. This signal x ₅ is the OR gate 31
6 to signal x ₉ , set number counter 5
The count of the counter 502 of 00 is incremented by 1, and the counters 308 and 408 are reset to complete one set.

On the other hand, as shown in FIG. 15, when one opponent wins 5 games first and then the other opponent immediately takes 5 games, the signals G _A5 and G _B5 output from the decoders 310 and 410 are both high. level, which causes the output signal of the NOR gates 312 and 412 to
x ₃ and x ₄ are kept at L level. Therefore, the AND gates 314 and 414 are closed, and even if whichever opponent takes the game points and wins 6 games first, the output signal of the AND gates 314 and 414 is
No pulses are generated at x ₅ and x ₆ . Then, when the game count is 6 to 5, one opponent raises the game point and the score becomes 7 to 5, and for example, the counter 3
When 08 counts up, this counter 30
8 output signal x ₇ becomes H level and OR gate 3
16, the count of the counter 502 of the set number counter 500 is incremented by one.

Further, as shown in FIG. 16, the game count changes from 6 to 5 to 6 to 6, and the tie-break display circuit 8
00 detects that a tie-break has occurred when the signals G _A6 and G _B6 go to H level, and sets the output signal F to L level. Therefore, the point counters 100, 200 described above do not output the signals _XA , _XB in response to the switch operation, and instead, the tie-break display circuit 800 (described later) outputs the operation signals A, B of the point input switches 34, 36. count to determine who is the winner of the tie-break. Therefore, this game number counter 300,
400 remains at a game count of 6 to 6 due to the absence of pulses on its input signals X _A and X _B . And the tie-break display circuit 800
When a pulse is generated in the signals U _A , U _B corresponding to the opponents output at the end of the tie-break, for example, signal U _A , this pulse is generated in _the signal The count of the counter 502 is incremented by one.

At this time, when the counter 502 of the set number counter 500 counts up, its output signal
x ₁₁ becomes H level and the set number counter 600
The signal _x14 is generated through the OR gate 606 of
This resets the counters 502, 602 and returns them to their initial states.

FIG. 17 is a diagram showing the circuit configuration of the advantage display circuit 700 shown in FIG. 1, and FIG. 18 is a time chart thereof.

This advantage display circuit 700 includes signals N _A output from the point counters 100 and 200,
A matching circuit 702 that detects matching between N _A10 and N _B and N _B10 , signals NB, NB ₁₀ , and memory 706
A matching circuit 704 that detects a match with "40" stored in , and these matching circuits 702 and 70
NAND gate 70 which inputs the output signals α ₁ and α ₂ of 4.
8 and a flip-flop 710 whose output state is switched by the output signal α ₃ of this NAND gate 708.
is provided. Furthermore, AND gates 712 and 714 are opened and closed by the signal α ₄ from the output Q of the flip-flop 710, and the output signals α ₅ and α ₆ of the AND gates 712 and 714 are input to the clock inputs of the AND gates 716 and 718. Flip-flops 720 and 722 input to φ, OR gates 724 and 726 that reset the flip-flops 720 and 722, and signals α ₅ , α ₆ and C _A ,
AND gates 728, 7 that input C _B respectively
30, flip-flops 732, 734 which input the output signals of the AND gates 728, 730 to the clock input φ, and the flip-flop 73.
The signal from the output Q of 2,734 causes the signal P _A ,
One-shot multivibrators 736 and 738 output P _B , and an OR gate 740 resets each flip-flop using the signals P _A and P _B.
Also provided. Also, the output of flip-flop 722 via inverter 717 is input to AND gate 716, and the output of flip-flop 720 via inverter 719 is input to AND gate 718.

This advantage display circuit 700 receives signals N _A and N _A10 from point counters 100 and 200.
The matching circuit 702 indicates that N _B and N _B10 match.
Detected by the signal N _B , N _B10 and memory 7
The match circuit 70 confirms that the stored contents of 06 match.
When the output signal α ₃ of the NAND gate 708 becomes L level and the output Q of the flip-flop 710 becomes H level, it is detected that the flip-flop 710 has become unused. When it becomes unused in this way, the signal R from the output of the flip-flop 710 goes to the L level, thereby preventing the point counters 100 and 200 from receiving the operation signals A and B from the point input switches 34 and 36. , operation signals A and B are sent via AND gates 712 and 714, which are now open instead.
is applied to the advantage display circuit 700.

The pulses generated in the output signals α ₅ and α ₆ of the AND gates 712 and 714 are applied to the clock input φ of the flip-flops 720 and 722, respectively, and are applied to the reset input R of the flip-flops 722 and 720 via the OR gates 726 and 724.
As shown in Figure 18,
A pulse is generated in the signal α ₅ and the flip-flop 72
The output Q of 0 becomes H level and the AND gate 72
Even if gate 8 becomes open, the next time a pulse is generated in signal α ₆ , flip-flop 720 is reset, and therefore AND gate 728 becomes closed again. Therefore, no pulse will occur in the output signal α ₉ or α ₁₀ of the AND gate 728 or 730 unless two pulses occur following the signal α ₅ or α ₆ in the initial state. When a pulse is generated in the signal α ₉ or α ₁₀ , the output Q of the flip-flop 732 or 734 becomes H level, and a pulse is output from the one-shot multivibrator 736 or 738 to inform other circuits that deuse has ended.

Furthermore, if one of the opponents obtains one point during deuse, the flip-flop 72 will be activated as described above.
The output Q of 0 or 722 becomes H level, and the signals C _A and C _B from the output Q at this time are sent to the driver 1400.
(FIG. 1), the point display of the person who has gained an advantage flashes to notify that the person has an advantage.

FIG. 19 is a diagram showing the circuit configuration of the tiebreaker display circuit 800, and FIGS. 20 and 21 are time charts thereof.

This tie-break display circuit 800 receives signals G _A6 output from the game number counters 300 and 400,
An AND gate 802 which becomes open when G _B6 is input and the game count becomes 6 to 6, a one-shot multivibrator 804 which inputs its output signal and outputs a pulse, and whose output signal β ₁ is input to the clock input φ A tie-break detection circuit is provided which detects and holds that a tie-break has entered. Also, AND gates 808 and 81 are opened and closed by the signal β ₂ from the output Q of this flip-flop 806.
0 and its output signals β ₃ and β ₄ respectively to count the tie break point, and the count contents are converted into code signals E _A and E _B to select the hour digit. Decoders 816 and 818 that apply to the circuit 1100 and the minute digit selection circuit 1200 and counters 812 and 81
AND gates 820 and 822 output when the outputs of each stage of 4 are input and count ``6'', AND gates 824 and 826 output when ``7'' is counted, and AND gates 820 and 82
NAND gate 82 which inputs the output signals β ₇ and β ₈ of 2
A flip-flop 830 inputs the output signal β ₉ of 8 to the clock input φ, and AND gates 824 and 8
One shot multivibrator 8 with 26 outputs
32, 834 and is opened and closed by the output of flip-flop 830.
36 and 838, and AND gates 840 and 8 which are opened by the output Q of flip-flop 830 and generate signals β ₃ and β ₄ as output signals β ₁₄ and β _15, respectively.
42, flip-flops 844 and 846 which input these signals β ₁₄ and β ₁₅ to the clock input φ, and output signals β ₁₆ of these flip-flops 844 and 846,
AND gates 848, 85 opened and closed by β ₁₇
0, and signals β ₁₂ , β ₁₈ , β ₁₃ , and β ₁₉ and output signals β ₂₀ and β ₂₁ .
, flip-flops 856 and 858 for outputting signals U _A and U _B indicating tie-break points corresponding to each opponent from one-shot multivibrators 860 and 862, and an OR gate 86 for resetting each flip-flop and counter.
4, 866, 868, 870, and 872, and is also provided with a tie-break release circuit that releases the tie-break state from the count values of counters 812 and 814.

Furthermore, a hexadecimal counter 876 that inputs and counts signals β ₃ and β ₄ via an OR gate 874;
A flip-flop 878 inputs the count-up output signal β ₂₆ of this counter 876 to a clock input φ, and AND gates 880 and 8 for setting and resetting this flip-flop 878.
82 is also provided.

First, when the game count becomes 6 to 6, the signals G _A6 and G _B6 go to H level and the AND gate 80 is activated.
The output of flip-flop 806 also becomes H level, a pulse is output from one-shot multivibrator 804, and the signal β ₂ from output Q of flip-flop 806 becomes H level, resulting in a tie-break state. When this signal β ₂ becomes H level, AND gates 808, 8
10 is in the open state, and the pulses generated in the operation signals A and B are signals β ₃ and β ₄ , respectively, and are counted by counters 812 and 814, respectively.
The count contents are converted into code signals E _A and E _B by decoders 816 and 818 and applied to the hour digit selection circuit 1100 and the minute digit selection circuit 1200.

Further, one of the counters 812 and 814 counts point "7", and the output of the AND gate 824 inputting the output of the counter 812 becomes H level as shown in FIG. When the signal β 5 is output, the pulse generated in the signal β ₅ passes through the AND gate 836 and the OR gate 85 which are normally open.
2 to flip-flop 856. This flip-flop 856 sets its output Q to the H level by the pulse generated in the signal β ₂₀ , and the one-shot multivibrator 860 generates a pulse in its output signal U _A , so that one opponent can set after a tie-break. The fact that points have been raised is transmitted to the set number counter 500 via the game number counter 300 described above.

On the other hand, as shown in FIG.
AND gates 820 and 822 detect that 14 has counted "6", and their output signals β ₇ ,
_β8 rises to H level. Therefore, the output signal β ₉ of the NAND gate 828 becomes L level, and in synchronization with the falling of the signal β 9 , the output of the flip-flop 830 becomes L level, and the AND gate 836,
838 is closed, and AND gates 840 and 842 are opened instead. At this time,
When one opponent raises the 7th point, for example, a pulse is generated on signal β ₃ , and even if a pulse is generated on signal β ₅ , it is blocked because the AND gate 836 is closed, and instead flip flop 8
When the output Q of 44 becomes H level, AND gate 848 becomes open. Next, when the same opponent raises a point again, the pulse generated in signal β ₃ is applied to flip-flop 856 via AND gate 848 and OR gate 852, and a pulse is output from one-shot multivibrator 860, ending the tie-break. do. Also, the other opponent scores points and the points are 7 to 7.
, the pulse generated in the signal β ₄ resets the flip-flop 844 whose output Q was previously set to H level through the OR gate 870, and the output Q goes to the H level again.
The situation returns to the same as when it was 6 vs. 6, and if one of the opponents does not score 2 points in a row, the signal U _A
Or it is configured so that no pulse is generated on U _B.

During this tie-break, a court change is performed every sixth play, but this is because the pulses generated by both signals β ₃ and β ₄ are sent to the counter 876.
, and when it counts "6", a pulse is generated in its output signal β ₂₆ and the output signal J ₁ of flip-flop 878 becomes H level. When this signal _J1 becomes H level, the display is inverted by the display inverting circuit 900 described above.

This flip-flop 878 is set to the set state by the signal β ₂₄ when a tie-break occurs, and is reset to the initial state by the inverted signal J ₀ when in the normal point counting state.

FIG. 22 shows the hour digit selection circuit 110 shown in FIG.
0, minute digit selection circuit 1200, second digit selection circuit 130
FIG. 2 is a diagram showing a more detailed configuration of the driver 1400.

The time digit selection circuit 1100 receives the signals E _{A and} E B indicating the points of each opponent during the tie break outputted from the tie break display circuit 800 and switches the signals E _A and _{E B using} the inverted signal J. The output multiplexer 1102 and this multiplexer 11
a multiplexer 1104 which inputs the output of 02, a signal indicating one digit of the point outputted from the point counter 100, and N _A and switches and outputs these input signals by a signal F indicating a tie break;
A multiplexer 1106 inputs the output of this multiplexer 1104 and the 1 hour digit signal output from the hour digit counter 26, and switches and outputs the input signal using a switching signal Q, and a multiplexer 1106 that inputs the output of the multiplexer 1104 and the 1 hour digit signal output from the hour digit counter 26, and outputs the 10 hour digit signal H ₁₀ and the 10 digit of the point. A multiplexer 1108 is provided which inputs the signal N _A10 shown in FIG.

In addition, the minute digit selection circuit 1200 is supplied with signals E _A and E _B indicating points in the tiebreaker, and a multiplexer 12 that switches and outputs them using an inverted signal J.
02, the output of this multiplexer 1202, and the point output from the point counter 200.
Multiplexer 1 which inputs the signal N _B10 indicating 10 digits and switches the output by signal F indicating tie break.
204, the output of this multiplexer 1204, and the 10 minute digit signal M ₁₀ output from the minute digit counter 20.
A multiplexer 1206 is provided which inputs a 1-minute digit signal M and a signal N _B indicating one digit of a point and outputs the signal by switching the signal Q according to the switching signal Q.

Furthermore, the second digit selection circuit 1300 is input with both game number counters G _A and G _B , and a multiplexer 1302 which alternately switches and outputs them using an inverted signal J.
1304, a multiplexer 1306 which inputs the 10 seconds digit signal S ₁₀ outputted from the seconds digit counter 14 and the output of the multiplexer 1302 and switches the output by the switching signal Q, and the 1 seconds digit signal S and the multiplexer 13.
A multiplexer 1308 is provided which inputs the output of 04 and switches the output according to the switching signal Q.

In the time display state, that is, when the signal Q is at L level, the hour digit selection circuit 1100 outputs the 10 o'clock digit signal.
H ₁₀ and 1 hour digit signal H are output, and minute digit selection circuit 1
200 outputs a 10-minute digit signal M ₁₀ and a 1-minute digit signal M, and the seconds digit selection circuit 1300 outputs a 10-second digit signal.
S ₁₀ and 1 second digit signal S are output.

When counting tennis points, that is, when the signal Q is at H level, the hour digit selection circuit 1
From 100, 10 digit signal of one opponent's points
N _A10 and 1 digit signal N _A are output, minute digit selection circuit 1
From 200, the 10-digit signal of the other opponent's points
N _B10 and 1 digit signal N _B are output, seconds digit selection circuit 1
300 outputs signals G _A and G _B indicating the game count of each opponent.

When a court change is performed during a tennis game and the inversion signal J becomes H level, the multiplexers 1302 and 1304 of the seconds digit selection circuit 1300
The outputs of the seconds digit selection circuit 1300 switch between each other.
The left and right output signals are inverted and output.

In addition, in a tie-break state, that is, when the signal F becomes L level, the multiplexers 1104 and 120 of the hour digit selection circuit 1100 and the minute digit selection circuit 1200
4 is switched to output the output signals of the multiplexers 1102 and 1202, and when the inverted signal J becomes H level during the tie-break, the multiplexers 1102 and 1202 switch and output the output signals from each other.

On the other hand, driver 1400 includes digit drivers 1402, 1406,
1408, 1410, 1412, 1414, NAND gates 1414, 1416 which receive the signals C _A and C _B output from the advantage display circuit 700 and the clock signal φ, and the outputs of these NAND gates 1414, 1416 and the tie-break signal F. Input AND gates 1418, 1420
It is composed of. This digit driver 1402
~1412 usually input signals from each digit selection circuit to drive each day's segment, and the advantage signal C _A or C _B is input to the NAND gate 14.
14, 1416 is input and a clock signal φ is generated at its output, the digit driver 1402
~1408 are the glyph segments 4a, 4b,
6a and 6b are driven to blink. Further, when the tie-break signal F becomes L level, the AND gates 1418 and 1420 are closed, the digit drivers 1402 and 1408 are stopped, and the display corresponding to the digit drivers 1402 and 1408 is turned off.

FIG. 23 shows the day of the week digit selection circuit 150 shown in FIG.
0 is a diagram showing the configuration of 0.

This day of the week digit selection circuit 1500 selects the set number signal output from the set number counters 500 and 600.
Input all T _A1 ~ _{T B3} and connect the signals T _A1 ~ _{T A3} to each other.
Alternatively, input the multiplexers 1502 and 1504 that switch and output the signals T _B1 to _{T B3} using the inverted signal J, the output signals D ₁ to _{D 7} from the day of the week counter 32, and the outputs of the multiplexers 1502 and 1504, and switch them using the switching signal Q. Multiplexer 15 to output
06.

When the switching signal Q is at L level, day of the week signals D ₁ to D ₇ are output from the multiplexer 1506,
The driver 1600 lights up one segment in the corresponding day of the week display section 10. Also, switching signal Q
When is at H level, multiplexer 1502,
Set number signals T _A1 to T _A3 output from 1504,
Output each of T _B1 to T _B3 and drive the driver 1600.
The segments are lit to the left and right with the segment 10d as the border, corresponding to the set number.

Note that when the inverted signal J becomes H level, the signals output from the multiplexers 1502 and 1504 are exchanged with each other and output, so that the set number is displayed with the right and left swapped with the segment 10d as the border. .

In this way, in this embodiment, points, number of games, and number of sets are displayed, and it is possible to handle double use and tie-breaks, and furthermore, the game count, set count, etc. are configured to be reversed left and right at the time of court change. .

(Effects of the Invention) According to this embodiment, when the number of games obtained by the opponents becomes 6 to 6, the tie-break mode is automatically entered, and if a predetermined point is obtained, the set is automatically changed. The next set is started. This eliminates the need for the user to operate a switch each time a tiebreak is entered or terminated, making it extremely easy to use.
In addition, the tie-break point display is a single-digit display instead of the usual two-digit display, making it possible to see at a glance that a tie-break has entered. Furthermore, in this embodiment, all scores can be displayed using only the time display segment, so that it can be used in common with the time display section. Furthermore, at the time of a court change, the number of games and the number of sets or points during a tie-break are swapped left and right, so they can always be displayed in a way that corresponds to each opponent.

As described above, according to the present invention, it is possible to provide a tennis counter that automatically starts and cancels a tie-break and allows you to tell at a glance that a tie-break has occurred.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention, FIG. 2 is a diagram showing a segment arrangement of the display section shown in FIG. 1, and FIGS.
10 is a diagram showing the circuit configuration of the point counter and display inverting circuit shown in FIG. 1, and FIGS.
FIG. 13 is a diagram showing the circuit configuration of the game number counter and set number counter shown in FIG. 1, FIGS. 14 to 16 are time charts of the circuit shown in FIG. 13, Figure 17 is a diagram showing the circuit configuration of the advantage display circuit shown in Figure 1, Figure 18 is a time chart of the circuit shown in Figure 17, and Figure 19 is a diagram showing the circuit configuration of the tie-break display circuit shown in Figure 1. 20 and 21 are time charts of the circuit shown in FIG. 19,
22 is a diagram showing the circuit configuration of the hour digit selection circuit, minute digit selection circuit, second digit selection circuit and driver shown in FIG. 1, and FIG. 23 is a diagram showing the circuit configuration of the day digit selection circuit shown in FIG. 1. It is a diagram. 2... Display unit, 10... Oscillator, 12... Frequency divider, 14... Second digit counter, 20... Minute digit counter, 26... Hour digit counter, 32... Day of the week counter, 100, 200... Point counter, 30
0,400...game number counter, 500,60
0...Set number counter, 700...Advantage display circuit, 800...Tie break display circuit, 900...Display inversion circuit, 1000...Reset circuit, 1100...Hour digit selection circuit, 1200
...Minute digit selection circuit, 1300...Second digit selection circuit,
1400, 1600...driver, 1500...
Day of the week digit selection circuit.

Claims (1)

[Claims] 1 Two sets of point counters that count the number of points obtained by each opponent in a tennis game by operating an external switch, two sets of game counters that count the number of games obtained by each opponent, and the number of sets obtained by each opponent. two sets of set counters for counting, a point display section consisting of two digit display elements each for displaying each output of the point counters, a game display section for displaying the count output of each game counter, and a point display section for displaying each output of the point counters; A tennis counter comprising: a set display section for displaying count outputs of the counters; A tie-break counter that can count the number of operations of the external switch in response to a signal; and a tie-break counter that can count the number of times the external switch is operated; and a tie-break counter that displays the count output of the tie-break counter in place of the point counter's count output on the point display section by operating the tie-break detection circuit. a multiplexer that supplies an output; a driver that turns off at least one digit of each two-digit point display section according to the count output of the tie-break detection circuit; and one of the count outputs of the two point counters. A tie-break release circuit that releases the operation of the tie-break detection circuit when the count of the counter is "7" or more and a difference of "2" or more with respect to the other counter is detected. tennis counter.