JPH0442613A - logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to logic circuits, for example, SPL (SPL) installed in high-speed logic integrated circuit devices such as high-speed computers.
The present invention relates to a technique that is particularly effective for use in upper Pu5h-pull Logic) circuits.

[Conventional technology]

An NTL (Non Threshold Logic
c) There is a circuit. There is also a so-called SPL circuit in which the output emitter follower circuit of the NTL circuit is replaced with an active pull-down circuit.

As illustrated in FIG. 6, the SPL circuit includes a pair of output transistors T3 and T4 arranged in a totem pole configuration between the ground potential and the power supply voltage of the circuit. , capacitor CI
A differential signal of the emitter voltage of the input transistor T1, that is, a non-inverted output signal of the phase dividing circuit, is supplied through a differentiating circuit including a resistor R4 and a resistor R4. As a result, the output transistor T4 is provided with a transistor T2 whose base receives a predetermined bias voltage 8 between the ground potential of the 0 circuit which acts as an active pull-down circuit of the SPL circuit and the base of the output transistor T4. It will be done. This transistor T2 constitutes a bias circuit together with the resistor R4, and applies a bias voltage to the output transistor T4 immediately before it is turned on. This increases the sensitivity of the SPL circuit.

Regarding SPL circuits, for example, Japanese Patent Application Laid-Open No. 1-26102
It is described in Publication No. 4, etc.

[All to be Solved by the Invention] However, the inventors of the present application have discovered that the conventional SPL circuit as described above has the following problems. That is, in the SPL circuit shown in FIG. 6 above,
The bias voltage Vt applied to the base of the transistor T2 constituting the bias circuit is generated by a voltage generating circuit provided in common to the plurality of 5PLil paths, and is transmitted via a relatively long supply wiring. Also, compared to this bias voltage VB, which is considered to be at a relatively stable level, 5P
LI circuit voltage voltage V El! The potential of l fluctuates as the plurality of output transistors T4 are selectively turned on. For this reason, the actual value of the bias voltage v8 applied to the transistor T2 varies, and accordingly, increasing the sensitivity of the SPL circuit is limited.

An object of the present invention is to stabilize and optimize the bias voltage applied to the bias transistor of an SPL circuit.

Another object of the invention is to further enhance the sensitivity and high frequency characteristics of the SPL circuit.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, SPL installed in high-speed logic integrated circuit devices, etc.
Each of the circuits includes, for example, a resistance means provided between the ground potential of the circuit and the base of the bias transistor, and two resistance means provided in series between the base of the bias transistor and the voltage source of the circuit. A voltage generating circuit consisting of diodes is provided.

[for creation]

According to the above-described means, the substantial bias voltage applied to the bias transistor of the SPL circuit is stabilized,
Can be optimized. As a result, the sensitivity of the SPL circuit can be further increased and its high frequency characteristics can be improved.

[Example 1] FIG. 1 shows a circuit diagram of a first embodiment of an SPL circuit to which the present invention is applied. Based on the figure, an overview of the configuration and operation of the SPL circuit of this embodiment and its characteristics will be explained.

Note that the SPL circuit shown in the following embodiments is installed in a high-speed logic integrated circuit device such as a high-speed computer, although this is not particularly limited. Each circuit element that makes up the SPL circuit is
Although not particularly limited, it is formed on a single semiconductor substrate such as single-crystal silicon together with other circuit elements constituting a high-speed logic integrated circuit device. In the circuit diagrams below, the illustrated transistors (in this specification, bipolar transistors are simply referred to as transistors) are:
Although not particularly limited, all transistors are NPN type transistors.

In FIG. 1, the 5PLI circuit of this embodiment includes an input transistor TI that receives an input signal S, although the collector of the input transistor TI is not limited to this.
The emitter is coupled to the ground potential (first voltage source) of the circuit via the resistor R1.

The circuit voltage voltage VEE+ (
a second voltage source). As a result, the input transistor TI and resistors R1 and R2 are connected to SPL.
Configure the phase division circuit of the circuit. In this example,
Although the voltage voltage V EE I of the circuit is not particularly limited,
For example, it is set to a negative voltage voltage such as -2.Ov.

The SPL circuit further has a ground potential and a voltage source voltage V of the circuit.
A pair of output transistors T3 (first output transistor) and T provided in a totem pole configuration between EE1
4 (second output transistor), the base of the output transistor T3 is coupled to the inverting output node of the phase dividing circuit, that is, the collector of the input transistor Tl, and the base of the output transistor T4 is connected to the capacitor C TI is coupled to the non-inverting output node of the phase divider circuit, ie, the emitter of the input transistor TI. Voltage voltage V between the base of the output transistor T4 and the circuit
A resistor R4, which together with the capacitor CI constitutes a differential circuit, is provided between the capacitor EE + and the capacitor CI. Further, the commonly coupled emifters and collectors of output transistors T3 and T4 are coupled to the output terminal SO of the SPL circuit.

As a result, the output transistors T3 and T4 form a so-called push-pull output circuit, and the output transistor T3 and T4 form a so-called push-pull output circuit.
4, a capacitor Ct, and a resistor R3.
Acts as an active pull-down circuit for output transistor T3.

A bias transistor T2 is provided between the ground potential of the circuit and the base of the output transistor T4.

In this embodiment, a resistor R3 (first resistance means) is provided between the ground potential of the circuit and the base of the biasing transistor T2, and a resistor R3 (first resistor means) is provided between the base of the transistor T2 and the voltage source voltage VEEI of the circuit. is provided with two diodes DI and D2 in series form. These resistances R
3 and diodes DI and D2 are connected to the transistor T
A voltage generating circuit is configured to apply a predetermined bias voltage to 2. That is, when the absolute value of the circuit voltage voltage ■EEI is VEEI, and the forward voltage of the diodes DI and D2 is VDF, the bias voltage VB applied to the transistor T2 is Vs--(VEEI 2X
In this example, the diode Di
and D2 are formed based on NPN type bipolar transistors. Therefore, the bias voltage V1B changes the base-emitter voltage of the bipolar transistor to v
When Bε, Ve = −(WEEt 2 x VBE),
As a result, the transistor T2 has the voltage voltage V of the circuit.
A stable bias voltage Vs corresponding to the composite base-emitter voltage of the transistor T2 and the output transistor T4, which are substantially stacked in two stages, ie, 2×v8ε, is provided without being affected by variations in EE1 or process variations.

Transistor T2 is connected to resistor R4 that constitutes the above-mentioned differential circuit.
Together with this, a bias circuit for the output transistor T4 is configured. At this time, a bias voltage corresponding to the base-emitter voltage BM is applied to the output transistor T4. Therefore, the output transistor T4 is biased to the state immediately before being turned on. #As mentioned above, output transistor T4C via transistor T2
The applied bias voltage is the voltage supply voltage of the circuit V HE
It is made stable without being affected by fluctuations of 1 or process fluctuations, and its value is taken as the optimum value, that is, the base-emitter voltage VBE of the output transistor T4. As a result, the sensitivity of the SPL circuit is sufficiently increased and its high frequency characteristics are improved.

When the input signal SI is at a high level, the inverted output signal of the phase division circuit becomes a predetermined low level, and the non-inverted output signal becomes a predetermined high level. transistor T3
The rising edge of the non-inverted output signal is transmitted to the base of the output transistor T4 via a differentiating circuit consisting of a capacitor C1 and a resistor R4. Therefore, the output transistor T3 is turned off, and the output transistor T4 is temporarily turned on.

Therefore, the output signal SO of the SPL circuit is rapidly brought to a low level similar to the voltage voltage VEE+ of the circuit.

On the other hand, when the input signal 51 is set to low level, the inverted output signal of the phase division circuit becomes high level, and the non-inverted output signal becomes low level.

Similarly, the high level of the inverted output signal of the phase division circuit is
The signal is transmitted as it is to the base of the output transistor T3, and the falling change of the non-inverted output signal is transmitted to the base of the output transistor T4 via the differentiating circuit. Therefore, the output transistor T4 quickly turns off, and the output transistor T3 turns on instead. As a result, 5PLI! The output signal SO of the path is set to a high level like VIE.

In other words, the level of the output signal SO is selectively set to a high level based on the logic condition 5o-51, and the SPL circuit in FIG. 1 essentially functions as an inverter circuit.
function.

As described above, the SPL circuit of this embodiment includes a pair of output transistors T3 and T4 provided in a totem pole configuration between the ground potential of the circuit and the voltage source voltage V EE 1, and a predetermined bias voltage applied to the output transistor T4. In this embodiment, each includes a bias transistor T2 that provides a bias voltage VB, and a voltage generation circuit that provides a predetermined bias voltage VB to the bias transistor T2.
The voltage generating circuit is provided in series between the base of the transistor T2 and the circuit voltage voltage V (El), and N
The potential difference between the output voltage, that is, the bias voltage VB, and the circuit voltage supply voltage VEEI is determined by the fluctuation of the circuit voltage supply voltage VIE1 and the process. 2XV without being affected by fluctuations! It is considered to be IE. Therefore, the output transistor T4 is provided with a stable bias voltage corresponding to the optimum value, that is, its base-emitter voltage VIF. As a result, the sensitivity of the SPL circuit is further increased and its high frequency characteristics are enhanced.

Note that the diodes Di and D2 constituting the voltage generation circuit of the SPL circuit of this embodiment are composed of NPN bipolar transistors as described above. By preparing common circuit elements on the top and selectively combining these circuit elements according to the required transfer characteristics, 1. S P
We believe that it is effective to selectively configure L circuits or NTL circuits. As in this example, some bipolar transistors and resistors that make up the NTL circuit, for example,
Diodes DI and D2 for configuring the voltage generation circuit
In addition, by using it as the resistor R3, etc., it is possible to save the waste of providing a voltage generation circuit for each SPL circuit.

(Embodiment 2) FIG. 2 shows a circuit diagram of a second embodiment of the SPL circuit to which the present invention is applied. Although the SPL circuit of this embodiment is not particularly limited, This basically follows the embodiment shown in the figure, and the transistors T1 to Tj
, diodes Di and D2. Capacitor CI and resistors R1 to R4 are transistors Tl to Tj of FIG.

Diodes DI and D2. They correspond directly to the capacitor C1 and the resistors R1 to R4, respectively. Hereinafter, only the parts that are different from the embodiment shown in FIG. 1 will be explained.

In the second WJ, the SPL circuit is configured such that, although not particularly limited, the ground potential (first voltage source voltage) of the circuit and the voltage #l@voltage V
El! 1 and VEIL (second power supply voltage) are operated as tS. Among these, the voltage voltage VEE1 of the circuit is as follows:
The resistor R2 constituting the phase division circuit is terminated, and the emitter of the output transistor T4, the resistor R4, and the cathode of the diode D2 are terminated at the voltage source voltage V EE L of the circuit. In this example, the circuit voltage voltage V T
EE I is a negative li voltage voltage such as -2,OV, and the circuit voltage voltage εEL is not particularly limited, but -
3. It is assumed to be a negative voltage voltage such as OV.

As described above, the potential of the voltage V EE L of the circuit where the emitter of the output transistor T4 is terminated varies as the output transistor T4 having a relatively large conductance is selectively turned on. As in this embodiment, the operation of the SPL circuit is stabilized by separating the voltage voltage at which these output transistors T4 and the like are terminated from the operating power source of the phase division circuit receiving the input signal Sl. Needless to say (also in the 5PLIi path of this embodiment,
Some of the effects obtained by the embodiment of FIG. 1 above are also obtained.

[Embodiment 3] The third WJ is the third WJ of the SPL circuit to which the present invention is applied.
A circuit diagram of an embodiment is shown. SPL of this example
The circuit basically follows the embodiment shown in FIGS. 1 and 2 WJ, and the transistors T1 to Tj, the capacitor CI, and the resistors R1 and R2 are the same as the transistors Tl to Tj in FIGS. 1 and 2. and capacitor CI
and resistors R1 and R2, respectively. Hereinafter, only the parts that are different from the embodiments shown in FIGS. 1 and 2 will be explained.

In FIG. 3, although the SPL circuit is not particularly limited,
The ground potential of the circuit (first voltage source voltage) and the voltage source voltage Vrr(
(second voltage source voltage) and VEEI (third voltage source voltage) are used as operating power sources. Among these, the voltage voltage of the circuit V EE 1
A resistor R2 constituting a phase dividing circuit is terminated, and a voltage source VTT of the circuit is terminated by an emitter of an output transistor T4, a resistor R4, and a resistor R8 to be described later. Here, the voltage voltage VEEI of the circuit is a negative voltage voltage such as -2.OV, and the voltage voltage VTT of the circuit is, although not particularly limited, a negative voltage voltage such as -1.8V. It is considered as pressure. The absolute value of this voltage source voltage VTr corresponds to the absolute value of the voltage source voltage VTr of the NTLl path shown in FIG.
This allows the SPL circuit and the NTL circuit to be efficiently mounted together on the same semiconductor substrate.

In this embodiment, the voltage generation circuit for applying a predetermined bias voltage VB to the bias transistor T2 is as follows:
Although not particularly limited, a resistor R5 (first resistance means) provided between the ground potential of the circuit and the base of the transistor T2 is connected in series between the base of the transistor T2 and the circuit voltage VTT. A diode D4 and a resistor R8 (second resistance means) are provided. As a result, the value of the bias voltage VB applied to the transistor T2 is V, --R6XI, where the absolute value of the voltage #I voltage VTr of the circuit is vrr and the value of the current flowing in the voltage generating circuit is 11. 1 = -R6X (Vtr VIE) / (R6 in R5)
As is well known, the temperature characteristic PT of the current 11 is as follows, when the ambient temperature is Tj: PT-δII/δTj = (1/(R6 in R5))xδVai:/δTj. As a result, by setting the resistors R5 and R6 to appropriate resistance values, the bias voltage VB and its temperature characteristics can be arbitrarily set and optimized.

[Embodiment 4] FIG. 4 shows the fourth 5PLWA path to which this invention is applied
A circuit diagram of an embodiment is shown. SPL of this example
Although the circuit is not particularly limited to 1ilJ, it basically follows the embodiment shown in FIG. 3 above, and includes transistors Tl,
T3 and T4 and capacitor C1 and resistors R1 and R
2 is the transistor T1.2 of the third WJ. They correspond directly to T3 and T4, capacitor CI, and resistors R1 and R2, respectively. Hereinafter, only the parts that are different from the embodiment shown in FIG. 3 will be explained.

In FIG. 4, the 5PLI circuit does not include a bias transistor; instead, a resistor R7 (
a voltage generating circuit consisting of a diode D4 and a resistor R8 (a fourth resistor &) provided in series between the base of the output transistor T4 and the voltage voltage V of the circuit. Equipped with The SPL circuit is further provided between the base of the output transistor T4 and the non-inverting output node of the phase component M circuit and substantially connected to the diode D4.
and a capacitor C that constitutes a differential circuit together with a resistor R8.
1 (capacitive means), so that the output transistor T4 has:
Needless to say, by appropriately designing the resistance values of resistors R7 and R8, the bias voltage vB'' can be optimized along with its temperature characteristics, and the output transistor T4 is turned on. The value is set to the immediately previous value.Furthermore, by omitting the bias transistor, the configuration of the SPL circuit is simplified and its cost can be reduced.

As shown in the plurality of embodiments described above, the present invention can be applied to an S
By applying it to a PL circuit, the following effects can be obtained. That is, (1) each of the SPL circuits installed in a high-speed logic integrated circuit device, etc. includes, for example, a resistance means provided between the ground potential of the circuit and the base of the bias transistor; By providing a voltage generation circuit consisting of two diodes connected in series between the voltage source voltage of the circuit, it is possible to optimize the bias voltage applied to the bias transistor, and to eliminate fluctuations in the voltage source voltage and process variations. The effect of stabilization without being affected by this can be obtained.

(2) According to the above item (1), it is possible to further increase the sensitivity of the SPI circuit and improve its high frequency characteristics.

(In paragraphs <i) and (2) above, the voltage generating circuit of the SPL circuit is connected to the resistor means that is placed between the ground potential of the circuit and the base of the bias transistor, and the base of the bias transistor. By configuring the circuit with a diode and a resistor connected in series with the voltage source of the circuit, the temperature characteristics can be optimized and the bias voltage given to the bias transistor can be optimized. The effect is that the sensitivity can be further increased and the high frequency characteristics can be improved.

(4) Each of the SPL circuits installed in a high-speed logic integrated circuit device, etc. includes, for example, a resistance means provided between the ground potential of the circuit and the base of the output transistor transistor constituting the active pull-down circuit, and the output transistor By providing a voltage generating circuit consisting of a diode and a resistor connected in series between the base of the SPL circuit and the voltage source of the circuit, the configuration of the SPL circuit can be simplified and the bias voltage applied to the output transistor can be optimized. Therefore, it is possible to further improve the sensitivity and high frequency characteristics of the SPL circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIGS. 1 to 4W, the SPL circuit can have any number of inputs and any logical function by changing the number and connection form of the input transistors that constitute the phase division circuit. Also, SP
The L circuit can include a clamp circuit and a level holding circuit for stabilizing the level of the output terminal SO, and further includes another voltage generation circuit for applying a predetermined bias voltage to the transistors forming the clamp circuit. It is also possible to have The specific circuit configuration of the SPL circuit, combination of power voltages, conductivity type of transistors, etc.
Various embodiments are possible.

The above explanation has mainly been about the application of the invention made by the present inventor to the SPL circuit installed in high-speed logic integrated circuit devices, which is the field of application that formed the background of the invention, but the invention is not limited thereto. For example, the present invention can be applied to similar SPL circuits installed in gate array integrated circuits and various dedicated logic integrated circuit devices. It can be widely applied to logic circuits including logic circuits or semiconductor integrated circuit devices including such logic circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the S installed in high-speed logic integrated circuit devices, etc.
Each of the PL circuits includes, for example, a resistance means provided between the ground potential of the circuit and the base of the bias transistor, and two resistance means provided in series between the base of the bias transistor and the circuit @ source voltage. By providing a voltage generating circuit consisting of a diode and a diode, it is possible to stabilize and optimize the substantial bias voltage applied to the bias transistor. As a result, the sensitivity of the SPL circuit can be further increased and its high frequency characteristics can be improved.

[Brief explanation of drawings]

1 is a circuit diagram showing a first embodiment of an SPL circuit to which the present invention is applied; FIG. 2 is a circuit diagram showing a second embodiment of an SPL circuit to which the present invention is applied; FIG. 4 is a circuit diagram showing a third embodiment of the SPL circuit to which the present invention is applied. FIG. 4 is a circuit diagram to show the fourth embodiment of the SPL circuit to which the invention is applied. , @ Figure 6 is a circuit diagram showing an example of an NTL circuit installed in a high-speed logic integrated circuit device equipped with the SPL circuit shown in Figure 3 or Figure 4. Figure 6 is a circuit diagram showing an example of a conventional SPL circuit. It is. Tl-76...NPN type bipolar transistor, D
i-D4...Diode, C1...Capacitor, R
1-R11...Resistance. Figure 1 Figure 2 Figure Figure EEI TT Figure Figure ■εEr

Claims (1)

[Claims] 1. A phase dividing circuit that receives an input signal, and a first output that is provided between a first power supply voltage and an output terminal of the circuit and receives an inverted output signal of the phase dividing circuit at its base. a second output transistor provided between the output terminal of the circuit and a second power supply voltage; and a second output transistor provided between the non-inverting output node of the phase division circuit and the base of the second output transistor. a differentiating circuit, a bias transistor provided between the first power supply voltage and the base of the second output transistor, and a voltage generation circuit that applies a predetermined bias voltage to the bias transistor. A logic circuit that 2. The voltage generation circuit includes a first resistance means provided between a first power supply voltage and the base of the bias transistor, and a first resistance means provided between the base of the bias transistor and a second resistance means.
2. The logic circuit according to claim 1, further comprising a diode and/or second resistance means provided in series between the logic circuit and the power supply voltage. 3. The phase dividing circuit uses the first and third power supply voltages as operating power supplies, and the absolute value of the potential difference between the first and second power supply voltages is equal to the first and third power supply voltages. 3. The logic circuit according to claim 1, wherein the logic circuit is made smaller than the absolute value of the potential difference. 4. The logic circuit according to claim 1, 2, or 3, wherein the logic circuit is an SPL circuit installed in a high-speed logic integrated circuit device such as a high-speed computer. 5. a phase divider circuit that receives an input signal; a first output transistor that is provided between a first power supply voltage and an output terminal of the circuit and receives an inverted output signal of the phase divider circuit at its base; a second output transistor provided between an output terminal and a second power supply voltage; a capacitor provided between a non-inverting output node of the phase dividing circuit and a base of the second output transistor; a third resistance means provided between the first power supply voltage and the base of the second output transistor; and a third resistance means provided in series between the base of the second output transistor and the second power supply voltage. A logic circuit comprising a diode and a fourth resistance means. 6. The logic circuit according to claim 5, wherein the logic circuit is an SPL circuit installed in a high-speed logic integrated circuit device such as a high-speed computer.