JPH044344U - - Google Patents
Info
- Publication number
- JPH044344U JPH044344U JP4323490U JP4323490U JPH044344U JP H044344 U JPH044344 U JP H044344U JP 4323490 U JP4323490 U JP 4323490U JP 4323490 U JP4323490 U JP 4323490U JP H044344 U JPH044344 U JP H044344U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- address
- multiplexer
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案のパイプライン回路の構成ブロ
ツク図、第２図ははこのように構成されたパイプ
ライン回路の動作を説明するためのタイムチヤー
ト、第３図は従来のパイプライン回路の構成ブロ
ツク図、第４図は従来のパイプライン回路の動作
を説明するためのタイムチヤート。
１０…メモリ、２０…パイプライン回路、２１
…ラツチ、２２ｎ…シフトレジスタ、２３ｎ…入
力マルチプレクサ、２４…出力マルチプレクサ、
２５…マルチプレクサコントローラ。
Figure 1 is a configuration block diagram of the pipeline circuit of the present invention, Figure 2 is a time chart for explaining the operation of the pipeline circuit configured in this way, and Figure 3 is the configuration of a conventional pipeline circuit. The block diagram and FIG. 4 are time charts for explaining the operation of a conventional pipeline circuit. 10...Memory, 20...Pipeline circuit, 21
...Latch, 22n ...Shift register, 23n ...Input multiplexer, 24...Output multiplexer,
25...Multiplexer controller.
Claims (1)
ミングに応じ、データのアドレスをクロツク信号
で遅延させてメモリに与えるパイプライン回路に
おいて、 前記アドレスが直接に入力されて、前記アドレ
スをワンクロツク分だけ遅延する第１のラツチと
、 この第１のラツチを介して前記アドレスが入力
されるとともに、前記アドレスが直接に並列して
入力されるｎ個の入力マルチプレクサと、 このｉ個目（ｉ＝１〜ｎ）の入力マルチプレク
サの出力に直列に２ｉ個のラツチが接続され、２
ｉ個目のラツチの出力をｉ＋１個目の入力マルチ
プレクサに出力するｎ個のシフトレジスタと、 このｎ個のシフトレジスタの出力と第１のラツ
チの出力を選択する出力マルチプレクサと、 前記入力マルチプレクサ及び前記出力マルチプ
レクサのスイツチを切換えてシフトレジスタの接
続数を可変し、メモリに出力されるアドレスの遅
延時間を任意に制御するマルチプレクサコントロ
ーラと、 を設けたことを特徴としたパイプライン回路。[Claims for Utility Model Registration] In a pipeline circuit that delays the address of data using a clock signal and supplies it to the memory according to the input timing of data to be written into the memory, the address is directly input and the address is a first latch that delays the address by one clock; n input multiplexers to which the address is input via the first latch and input directly in parallel; 2 i latches are connected in series to the outputs of input multiplexers (i = 1 to n), and 2
n shift registers that output the output of the i -th latch to the i+1-th input multiplexer; an output multiplexer that selects the output of the n shift registers and the output of the first latch; the input multiplexer; and A pipeline circuit comprising: a multiplexer controller that changes the number of connected shift registers by switching a switch of the output multiplexer and arbitrarily controls a delay time of an address output to a memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4323490U JPH044344U (en) | 1990-04-23 | 1990-04-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4323490U JPH044344U (en) | 1990-04-23 | 1990-04-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH044344U true JPH044344U (en) | 1992-01-16 |
Family
ID=31555479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4323490U Pending JPH044344U (en) | 1990-04-23 | 1990-04-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH044344U (en) |
-
1990
- 1990-04-23 JP JP4323490U patent/JPH044344U/ja active Pending
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