JPH044453A - Distributed-processor control system - Google Patents

Abstract

PURPOSE:To reduce communication loads to CPUs between processors by controlling the actual transfer of information data between the processors under the control of a direct memory access controller. CONSTITUTION:A host processor 1 contains a higher-rank communication memory 3, higher-rank transfer control circuit 4, and higher-rank interrupt control circuit 5 and a slave processor 16 contains a lower-rank communication memory 18, lower-rank transfer control circuit 19, and lower-rank interrupt control circuit 20. A direct memory access controller 11 in a control interface 9 controls the transfer of information data through a memory for communication 10 between the memories 3 and 18 on the basis of a transfer request, issuance of a transfer completion notice, etc., to the circuits 4 and 19. In addition, an interrupt control circuit 12 in the interface 9 controls the interrupt to the host processor 1 and a CPU 17 in the slave processor 16 on the basis of a transfer request notice, etc., to the circuits 5 and 20. Therefore, communication loads to CPUs between the processors can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a distributed processor control system, and particularly to a distributed processor control system that controls inter-processor communication between a higher-level processor and a lower-level processor.

[Conventional technology]

In a computer system such as an electronic switching system, a distributed processor control method is sometimes adopted in which processors controlling the computer system are functionally distributed. In this distributed processor control method, a computer system is configured by a group of hierarchical processors, and the number of lower processors is increased or decreased depending on the amount of load.

FIG. 2 is a block diagram showing the configuration of an example of a conventional distributed processor control system of this type.

The upper CPU (Cent
ral processing unit) 22 is connected to a communication memory 25 provided in a control interface 24 via an upper level bus 23. Furthermore, the communication memory 25 in the control interface 24 communicates with the lower CPO that constitutes the lower processor 27 via the lower lotus 26.
28.

When inter-processor communication is performed from the upper processor 21 to the lower processor 27, the upper CPU 22 in the upper processor 21 transmits information data (
data to be communicated between processors) is written to the communication memory 25 in the control ink face 24.

The lower CPU 28 in the lower processor 27 learns that the information data has been written to the communication memory 25, and reads the information data from the communication memory 25 via the lower bus 26.

Further, when inter-processor communication is performed from the lower processor 27 to the upper processor 21, similar processing is performed in the opposite direction to the above-described operation.

In this way, in the conventional distributed processor control method, when inter-processor communication occurs between an upper processor and a lower processor, the upper CPU in the upper processor or the lower CPU in the lower processor controls communication within the control interface. Memory was being accessed directly.

[Problem to be solved by the invention]

In the conventional distributed processor control method described above, when inter-processor communication occurs between an upper processor and a lower processor, the communication memory in the control interface is used by the upper CPU in the upper processor or the lower CPU in the lower processor. Since it is directly accessed, there is a drawback that the load on the CPU (lower CPU and lower CPU) in interprocessor communication increases.

In particular, when the number of lower processors is large, the time required for the upper CPU to engage in inter-processor communication increases, and the higher CPU
The above-mentioned shortcomings are serious.

In addition, because lower-level CPUs often have slow processing speeds due to price constraints, inter-processor communication time depends on the processing speed of the lower-level CPUs, which affects the higher-level CPUs.
Another drawback is that the time U (ie, the upper processor) is involved in interprocessor communication is extended.

In view of the above-mentioned points, an object of the present invention is to reduce the load on the CPU in inter-processor communication, and to
An object of the present invention is to provide a distributed processor control method that can reduce the time required for communication between processors (PU).

[Means to solve the problem]

The distributed processor control method of the present invention includes an upper processor including an upper communication memory, an upper transfer control circuit, and an upper interrupt control circuit; a lower processor including a lower communication memory, a lower transfer control circuit, and a lower interrupt control circuit; The transfer of information data via the communication memory (internal communication memory) between the upper-level communication memory and the lower-level communication memory is performed by a transfer request to the upper-level transfer control circuit and the lower-level transfer control circuit. A direct memory access controller that controls based on the issuance of a transfer completion notification, etc., and interrupt control for the CPU in the upper processor and the lower processor based on the notification of a transfer request to the upper interrupt control circuit and the lower interrupt control circuit, etc. and a control interface including an interrupt control circuit that performs.

[Effect]

In the distributed processor control method of the present invention, the upper processor includes an upper communication memory, an upper transfer control circuit, and an upper interrupt control circuit, and the lower processor includes a lower communication memory, a lower transfer control circuit, and a lower interrupt control circuit,
The direct memory access controller in the control interface controls the transfer of information data via the communication memory between the upper communication memory and the lower communication memory, and sends transfer requests and transfer completion notifications to the upper transfer control circuit and the lower transfer control circuit. The interrupt control circuit in the control interface performs interrupt control for the CPUs in the upper processor and lower processor based on the notification of transfer requests to the upper interrupt control circuit and the lower interrupt control circuit.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the distributed processor control system of the present invention. In the distributed processor control method of this embodiment, the upper processor 1, the upper bus 6,
Upper transfer control lead 7, upper interrupt control lead 8,
It is configured to include a control interface 9, a lower bus 13, a lower transfer control lead 14, a lower interrupt control lead 15, and a lower processor 16.

The upper processor 1 includes an upper CPU 2, an upper communication memory 3, an upper transfer control circuit 4, and an upper interrupt control circuit 5.
It is composed of:

A control interface 9 that is located between the upper processor 1 and the lower processor 16 and mediates between them includes a communication memory 10 and a direct memory access controller 11.
and an interrupt control circuit 12.

The lower processor 16 includes a lower CPU 17, a lower communication memory 18, a lower transfer control circuit 19, and a lower interrupt control circuit 20.

The upper communication memory 3 and the communication memory 10 are connected to the upper bus 6.
The communication memory 10 and lower-order communication memory 18 are connected via a lower-order bus 13.

The upper transfer control circuit 4 and the direct memory access controller 11 are connected via the upper transfer control lead 7, and the direct memory access controller 11 and the lower transfer control circuit 19 are connected via the lower transfer control lead 14.

The upper interrupt control circuit 5 and the interrupt control circuit 12 are connected via the upper interrupt control lead 8, and the interrupt control circuit 1
2 and the lower interrupt control circuit 20 are connected via the lower interrupt control lead 15.

Next, the operation of the distributed processor control system of this embodiment configured as described above will be explained.

When inter-processor communication is performed from the upper processor 1 to the lower processor 16, the upper CPU 2 in the upper processor 1 stores information data (hereinafter referred to as target information data) of the object of the inter-processor communication in the upper communication memory 3. ) is written, the upper transfer control circuit 4 is activated, and the upper transfer control circuit 4 issues a transfer request to the direct memory access controller 11 in the control interface 9 via the upper transfer control lead 7. After issuing the transfer request to the direct memory access controller 11 in this manner, the host CPU 2 is no longer involved in inter-processor communication processing and performs other processing.

After receiving the transfer request from the higher-level transfer control circuit 4, the direct memory access controller 11 obtains the right to use the higher-level bus 6 and transfers the target information data from the higher-level communication memory 3 to the communication memory 10. In other words, this transfer is performed without the intervention of the host CPU 2.

When the transfer of the target information data is completed, the direct memory access controller 11 notifies the upper transfer control circuit 4 of the completion of the transfer via the upper transfer control lead 7.

On the other hand, the interrupt control circuit 12 in the control interface 9 connects the lower processor 1 via the lower interrupt control lead 15.
A transfer request is made to the lower interrupt control circuit 20 in 6.

The lower-order interrupt control circuit 20 issues an interrupt to the lower-order CPUI 7 and notifies the above-mentioned transfer request.

When the lower CPU 17 receives the transfer request, the lower transfer control circuit 19 issues transfer permission to the direct memory access controller 11 in the control interface 9 via the lower transfer control lead 14.

After receiving the transfer permission, the direct memory access controller 11 obtains the right to use the lower-level bus 13 and transfers the target information data from the communication memory 10 to the lower-level communication memory 18. This transfer is performed regardless of the operating state of the lower CPU 17.

When the transfer of the target information data is completed, the direct memory access controller 11 notifies the lower transfer control circuit 19 of the completion of the transfer via the lower transfer control lead 14.

After receiving this transfer completion notification via the lower-order transfer control circuit 19, the lower-order CPU 17 can read the target information data from the lower-order communication memory 18.

When inter-processor communication is performed from the lower processor 16 to the upper processor 1, similar processing is performed in the opposite direction to the above operation, and the actual transfer of information data is performed by the CPUs (upper CPU 2 and lower CPU 17). Interprocessor communication is handled without intervention.

〔Effect of the invention〕

As described above, the present invention comprises an upper processor including an upper communication memory, an upper transfer control circuit, and an upper interrupt control circuit, and a lower processor including a lower communication memory, a lower transfer control circuit, and a lower interrupt control circuit. , a communication memory, a direct memory access controller, and a control interface including an interrupt control circuit are provided, and the actual transfer of information data between processors is performed under the control of the direct memory access controller. The CPU and the lower CPU in the lower processor can execute other processing without being substantially involved in processing during inter-processor communication, and there is an effect that the load on the CPU during inter-processor communication can be reduced.

Particularly, when there are many lower-level processors, the time required for communication between the higher-level processors and the processors can be significantly reduced, and the above-mentioned effect becomes remarkable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of an example of a conventional distributed processor control system. In the figure, 1...Upper processor, 2...Upper CPU, 3...Upper communication memory, 4...Upper transfer control circuit, 5...Upper interrupt control circuit, 6...Upper lot lot , 7... Upper transfer control read, 8... Upper interrupt control read, 9... Control interface, 10... Communication memory, 11... Direct memory access controller, 12... Interrupt control circuit, 13.・Lower lotus, 14.. Lower transfer control read, 15.. Lower interrupt control read, 16.. Lower processor, 17.. Lower CPU, 18.. Memory for lower order communication, 19.. Lower transfer control circuit, 20. - Lower interrupt control circuit.

Claims (1)

[Claims] An upper processor including an upper communication memory, an upper transfer control circuit, and an upper interrupt control circuit, a lower communication memory,
Transfer of information data via a communication memory between a lower processor including a lower transfer control circuit and a lower interrupt control circuit, and the upper communication memory and the lower communication memory is performed by the upper transfer control circuit and the lower transfer control circuit. a direct memory access controller that performs control based on transfer requests to circuits, issuance of transfer completion notifications, etc.; 1. A distributed processor control system comprising: a control interface including an interrupt control circuit that performs interrupt control for a CPU in a processor.