JPH0446740U - - Google Patents

Info

Publication number
JPH0446740U
JPH0446740U JP8860290U JP8860290U JPH0446740U JP H0446740 U JPH0446740 U JP H0446740U JP 8860290 U JP8860290 U JP 8860290U JP 8860290 U JP8860290 U JP 8860290U JP H0446740 U JPH0446740 U JP H0446740U
Authority
JP
Japan
Prior art keywords
buffer memory
received data
control device
clock signal
transmitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8860290U
Other languages
English (en)
Other versions
JP2588514Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990088602U priority Critical patent/JP2588514Y2/ja
Priority to EP91114022A priority patent/EP0473059B1/en
Priority to DE69132236T priority patent/DE69132236T2/de
Publication of JPH0446740U publication Critical patent/JPH0446740U/ja
Priority to US08/316,830 priority patent/US5430844A/en
Application granted granted Critical
Publication of JP2588514Y2 publication Critical patent/JP2588514Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例の構成を示すブロツク
図、第２図は実施例における動作を説明するため
のメモリマツプである。 １，２……通信回線、３……通信制御装置、５
……トランスミツタ、６……レシーバ、８……バ
ツフアメモリ、９……ＣＰＵ、１２……ＤＭＡコ
ントローラ、１３……アドレスカウンタ、１５，
１６，１７……バスドライバ。

Claims (1)

    【実用新案登録請求の範囲】
  1. ホストと通信回線の間に設けられた通信制御装
    置において、送信または受信データを一時記憶す
    るバツフアメモリと、該バツフアメモリに対する
    前記送信または受信データの読み出しあるいは書
    き込みを制御するＤＭＡコントローラと、該ＤＭ
    Ａコントローラから出力されるクロツク信号をカ
    ウントして所定値に達したとき制御信号を発生し
    、その内容により前記バツフアメモリをアドレス
    指定するアドレスカウンタとを備え、前記制御信
    号に応じてＤＭＡ動作を終了することを特徴とし
    た通信制御装置。
JP1990088602U 1990-08-22 1990-08-24 通信制御装置 Expired - Fee Related JP2588514Y2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1990088602U JP2588514Y2 (ja) 1990-08-24 1990-08-24 通信制御装置
EP91114022A EP0473059B1 (en) 1990-08-22 1991-08-21 Communication control system
DE69132236T DE69132236T2 (de) 1990-08-22 1991-08-21 Übertragungssteuerungssystem
US08/316,830 US5430844A (en) 1990-08-22 1994-10-03 Communication control system for transmitting, from one data processing device to another, data along with an identification of the address at which the data is to be stored upon reception

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990088602U JP2588514Y2 (ja) 1990-08-24 1990-08-24 通信制御装置

Publications (2)

Publication Number Publication Date
JPH0446740U true JPH0446740U (ja) 1992-04-21
JP2588514Y2 JP2588514Y2 (ja) 1999-01-13

Family

ID=31821950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990088602U Expired - Fee Related JP2588514Y2 (ja) 1990-08-22 1990-08-24 通信制御装置

Country Status (1)

Country Link
JP (1) JP2588514Y2 (ja)

Also Published As

Publication number Publication date
JP2588514Y2 (ja) 1999-01-13

Similar Documents

Publication Publication Date Title
JPS6421443U (ja)
JPS6034648U (ja) マイクロコンピユータにおけるメモリ・ページング・システム
JPH0446740U (ja)
JPH01173857U (ja)
JPS6446840U (ja)
JPH0452252U (ja)
JPH02149448U (ja)
JPS62158566U (ja)
JPH01125637U (ja)
JPH0353056U (ja)
JPS61164551U (ja)
JPH0181794U (ja)
JPH0184152U (ja)
JPH0324765U (ja)
JPS61128748U (ja)
JPH0458766U (ja)
JPH03117953U (ja)
JPS60640U (ja) Ｄｍａ処理とプログラム計測モ−ドの並行処理システム
JPH0256693B2 (ja)
JPS63171846U (ja)
JPH0377544U (ja)
JPH0865316A (ja) データ送受信装置
JPS6330048U (ja)
JPS59118048U (ja) 双方向ダイレクトメモリアクセス転送回路
JPS6168586U (ja)

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees