JPH0446740U - - Google Patents
Info
- Publication number
- JPH0446740U JPH0446740U JP8860290U JP8860290U JPH0446740U JP H0446740 U JPH0446740 U JP H0446740U JP 8860290 U JP8860290 U JP 8860290U JP 8860290 U JP8860290 U JP 8860290U JP H0446740 U JPH0446740 U JP H0446740U
- Authority
- JP
- Japan
- Prior art keywords
- buffer memory
- received data
- control device
- clock signal
- transmitted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Bus Control (AREA)
- Computer And Data Communications (AREA)
- Communication Control (AREA)
Description
第１図は本考案の実施例の構成を示すブロツク
図、第２図は実施例における動作を説明するため
のメモリマツプである。
１，２……通信回線、３……通信制御装置、５
……トランスミツタ、６……レシーバ、８……バ
ツフアメモリ、９……ＣＰＵ、１２……ＤＭＡコ
ントローラ、１３……アドレスカウンタ、１５，
１６，１７……バスドライバ。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a memory map for explaining the operation of the embodiment. 1, 2...Communication line, 3...Communication control device, 5
...Transmitter, 6...Receiver, 8...Buffer memory, 9...CPU, 12...DMA controller, 13...Address counter, 15,
16, 17... bus driver.
Claims (1)
置において、送信または受信データを一時記憶す
るバツフアメモリと、該バツフアメモリに対する
前記送信または受信データの読み出しあるいは書
き込みを制御するＤＭＡコントローラと、該ＤＭ
Ａコントローラから出力されるクロツク信号をカ
ウントして所定値に達したとき制御信号を発生し
、その内容により前記バツフアメモリをアドレス
指定するアドレスカウンタとを備え、前記制御信
号に応じてＤＭＡ動作を終了することを特徴とし
た通信制御装置。 A communication control device provided between a host and a communication line, comprising: a buffer memory for temporarily storing transmitted or received data; a DMA controller for controlling reading or writing of the transmitted or received data to the buffer memory;
and an address counter that counts the clock signal output from the A controller and generates a control signal when it reaches a predetermined value, and specifies an address for the buffer memory according to the content of the clock signal, and terminates the DMA operation in response to the control signal. A communication control device characterized by:
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990088602U JP2588514Y2 (en) | 1990-08-24 | 1990-08-24 | Communication control device |
| EP91114022A EP0473059B1 (en) | 1990-08-22 | 1991-08-21 | Communication control system |
| DE69132236T DE69132236T2 (en) | 1990-08-22 | 1991-08-21 | Transmission control system |
| US08/316,830 US5430844A (en) | 1990-08-22 | 1994-10-03 | Communication control system for transmitting, from one data processing device to another, data along with an identification of the address at which the data is to be stored upon reception |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990088602U JP2588514Y2 (en) | 1990-08-24 | 1990-08-24 | Communication control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0446740U true JPH0446740U (en) | 1992-04-21 |
| JP2588514Y2 JP2588514Y2 (en) | 1999-01-13 |
Family
ID=31821950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990088602U Expired - Fee Related JP2588514Y2 (en) | 1990-08-22 | 1990-08-24 | Communication control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2588514Y2 (en) |
-
1990
- 1990-08-24 JP JP1990088602U patent/JP2588514Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2588514Y2 (en) | 1999-01-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |