JPH0447420A - Ready circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ready circuit that synchronizes and outputs an asynchronous ready signal.

[Conventional technology]

FIG. 3 is a circuit diagram showing a general ready circuit that synchronizes and outputs an asynchronous ready signal, and FIG. 4 is a timing diagram for explaining the operation of the circuit shown in FIG. 3. In FIG. 3, 3 is a flip-flop circuit, 2 is an inverter, and 4 is an AND gate. Also, in Fig. 4, f
al represents the clock CLK (one cycle from Tl to T4), the peak) represents the asynchronous ready signal ARDY, (C) represents the output signal PRDY of the AND gate 4, and (d) represents the synchronized ready signal READY.

Next, the operation will be explained. In FIG. 3, the flip-flop circuit uses two stages and an AND gate in order to prevent malfunctions due to metastable operation due to insufficient set-up time of the asynchronous ready signal ARDY.

The synchronous ready signal is sampled at the falling edge A of the clock CLK in FIG. 4 (al), but when the asynchronous ready signal ARDY in FIG. After being sampled by the flip-flop circuit 3 at the rising edge B of the clock, it passes through an AND gate 4 which receives the asynchronous ready signal ARDY and the Q output of the flip-flop circuit 3, and is sampled at the timing of the rising edge A of the clock CLK. Ru.

[Problem to be solved by the invention]

Since the conventional ready circuit that synchronizes and outputs the asynchronous ready signal is configured as described above, the asynchronous ready signal must be sampled 1/2 clock before the sampling time of the synchronous ready signal. However, there was a problem in that it was difficult to ensure cent up time with respect to the clock.

The present invention has been made in view of these points, and its purpose is to obtain a ready circuit that can reduce the amount of hardware and alleviate the cent up time of an asynchronous ready signal with a simple circuit configuration. It is in.

[Means to solve the problem]

In order to achieve such an object, the present invention includes a schmint trigger circuit for preventing malfunctions due to metastable operation.

[Effect]

The ready circuit according to the present invention has one flip-flop circuit.
It is sampled at the same timing as the synchronous ready signal.

Embodiment C] FIG. 1 is a circuit diagram showing an embodiment of a ready circuit according to the present invention. In the figure, 1 is a flip-flop circuit, 2 is an inverter, and 5 is a Schmitt trigger circuit.

FIG. 2 is a timing diagram for explaining the operation of the circuit in FIG. 1, in which FIG. 2(a) shows the clock CLK, FIG. Indicates a synchronized ready signal READY.

Next, the operation will be explained. In FIG. 1, the asynchronous ready signal ARDY is sampled by the flip-flop circuit 1 at the falling edge A of the clock CLK, as shown in FIGS. 2(a) and (b), to prevent malfunctions due to metastable operation. A synchronized ready signal READY is output through the trigger circuit 5.

Therefore, since it is possible to sample the asynchronous ready signal at the same timing as the synchronous ready signal, sampling 1/2 clock earlier is not necessary, and the setup time can be reduced.

In the above embodiment, the Schmitt trigger circuit 5 is added as a separate port to prevent malfunctions due to metastable operation, but the same effect can be expected even if it is built into the flip-flop circuit 1.

〔Effect of the invention〕

As explained above, the present invention provides an asynchronous ready signal at the same timing as the synchronous ready signal by providing a Schmitt trigger circuit as a circuit for preventing malfunction due to metastable operation in a ready circuit that synchronizes and outputs an asynchronous ready signal. Since the signal can be sampled, the set amplifier time for the asynchronous ready signal relative to the clock can be reduced. Furthermore, since it can be configured with one stage of flip-flop circuits, a Schmint trigger circuit, and an inverter, it has the advantage of being able to have a simple circuit configuration with a reduced amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a ready circuit according to the present invention, FIG. 2 is a timing diagram for explaining the operation of the circuit in FIG. 1, and FIG. 3 is a circuit diagram showing a general ready circuit. ,
FIG. 4 is a timing diagram for explaining the operation of the circuit of FIG. 3. 1...Flip-flop circuit, 2...Inverter,
3...Schmitt trigger circuit.

Claims (1)

[Claims] 1. A ready circuit that synchronizes and outputs an asynchronous ready signal, the ready circuit comprising a Schmitt trigger circuit for preventing malfunctions due to metastable operation.