JPH0447582A - Searching method - Google Patents

Abstract

PURPOSE:To accurately perform search without increasing searching speed by performing the search by reducing tape speed by stages and reading a program number starting from a high-order digit. CONSTITUTION:A digital audio signal of N(N:integer bits and a digital video signal of M(M:integer) bits are synthesized, and synthesized signal is recorded on a tape as a digital signal of (N+M) bits, and the program number of plural digits is recorded on the tape at every digital video signal of one picture, and a targeted program number can be supplied. When the position of the program number is searched, the search is performed by reducing the tape speed to the one readable up to the prescribed high-order digit of the program number by stages. In such a way, the search can be accurately performed without extending search time so long.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a digital signal that is a combination of a digital audio signal and a digital video signal, and a multi-digit program is recorded for each screen of the digital video signal. This invention relates to a method of searching for the position of a target program number from a tape on which numbers are recorded.

[Prior art] The current digital audio tape recorder (hereinafter referred to as "D")
(referred to as "AT") is designed to record and reproduce only audio signals.

However, since it would be very convenient to record and play back not only audio signals but also other signals, such as video signals for still images, the applicant first synthesized digital audio signals and digital video signals. , proposed simultaneous recording and playback.

[Problem M to be solved by the invention] By the way, image data for multiple sides is recorded on a magnetic tape. For example, as will be described later, when MTS data for one screen is recorded in about 5 seconds. , a two-dose time tape for DAT, with over 1400 screens of image data recorded.

Therefore, it has been considered to record a four-digit program number 1 in the sub-coat section and use it for searching image data.

In this case, a 4-digit program number will be recorded approximately every 5 seconds, but when performing a 200x search, for example, the head will scan across multiple tracks, or the sub-coat area will be located at both ends of the recording track. For reasons such as the fact that there is only one program number, a recording time of about 9 seconds is required to accurately read the program number.

Therefore, when a 4-digit program number is recorded approximately every 5 seconds, the 200x search conventionally used in DAT cannot be used as is.

Note that if the tape speed is slowed down, searching is possible, but the search time becomes longer.

Therefore, in the present invention, it is possible to perform an accurate search without increasing the search time so much.

[Means for Solving the Problems] The present invention combines an N-bit (N is an integer) digital audio signal and an M-bit (M is an integer) digital video signal to produce an N+M-bit digital signal on a tape. A multi-digit program number is recorded on the tape for each screen of the digital video signal, a target program number is given, and when searching for that position on the tape, the tape speed is increased to a predetermined upper predetermined digit of the program number. The search is performed by gradually decreasing the reading speed.

[Function] As described above, when a 4-digit program number is recorded approximately every 5 seconds, first, for example, a 200x search is performed to search for the target program number up to 3 digits. here,
Considering a 3-digit program number, it takes about 50 seconds to record the same number, and it can be read accurately. next,
For example, a 16x search is performed to search for the position of the target program number. With 16x search, accurate search is possible even with a recording time of about 5 seconds.

By performing the search while decreasing the tape speed stepwise in this manner, the search can be performed accurately without increasing the search time.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

In this example, the analog audio signal is 1 sample 1
0-bit digital audio signal DSa [A9~
The signal is converted into AOI (shown in FIG. 2A) and further converted into a one-sample 8-bit digital audio signal DSa' [
A? '~AO'] (as shown in Figure B)
.

Further, the analog video signal is a digital audio signal DSv[V7 to V] of 8 bits per sample.

] (as shown in Figure C).

The second diagram shows the format of the digital signal DS recorded and reproduced in this example.

Among the 16-bit data DI5 to DO, the upper 8 bits contain digital audio signals DSa'[A7' to A
O'] is arranged, and a digital video signal DSv[V7 to VOI is arranged in the lower 8 bits.

A digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown) provided on the DAT, is recorded on a magnetic tape, and is reproduced from the magnetic tape.

As will be described later, in the DAT, both the left (L) channel and right (R) channel digital audio signals DSa sampled at the clock fs are sequentially recorded. Therefore, each sample data of the digital video signal DSv is mixed with the digital audio signal DSa and recorded in synchronization with the clock 2fs.

48kHz as audio sampling clock fs
Using , the video sampling clock is set to 4 f
sc (NTSC method, fsc is 3.58MH
z), the video sampling clock 4 f
There is a frequency difference of about 149 times between sc and the clock 2fs described above. In other words, 1/
Each sample data of the digital video I word DSV sampled at a period of 4 f sc is 1/2 fs (
The data are sequentially recorded at a period of about 149 times 1/4fsc).

Therefore, the distance between one frame and another is 1/30 second, so 1
It will take approximately 4.96 seconds to record a frame (odd and even fields) of video signal. Moreover, as will be explained later, the video signal has an identification code F.
' Since the ID is added, it takes about 5 seconds to finally record one frame of video signal.

FIG. 3 is a diagram showing the data structure. In other words, immediately before the video signal of each of the odd (ODD) and even (EVEN) fields that make up one screen, there is a start code S-ID indicating the start of data, and a start code S-ID to distinguish between odd and even fields. Mode code MD-I
D. A last start coat LS/ID is added to distinguish the identification code from the data. Immediately after the video signal of each field, a start code E-ID indicating the end of data is added (1).

For example, the start code):'S-ID is composed of 8-bit data with only the lowest hit being "1", and the stop code E/ID is composed of 8-bit data with all bits being "0". Ru.

FIG. 1 shows an example of a signal processing device for forming a digital signal DS in the format shown in FIG. 2 and recording and reproducing it on a DAT with the data structure shown in FIG.

First, the signal processing system for audio signals will be explained.

The left and right channel audio signals S aL and S aR supplied to the audio in terminals 8L and 8R are amplified by amplifiers 9L and 9R, and then sent to the noise reduction circuit 1.
Noise is removed using the 0LS IOR, and the band is limited using the low pass filters IIL and IIR.

Then, it is supplied to the A/D converters 12L and 12R.
Bit digital audio signal DSaL.

Converted to DSaR. The A/D converters 12L and 12R are equipped with an audio sampling clock fs (48kHz).
z) is supplied.

The digital audio f-words DSaL and DSaR output from the A/D converters 12L and 12R are supplied to the L side of the changeover switch 13 and RII, respectively.

This changeover switch 13 is supplied with a clock LRCK having a frequency of 48kHz and a duty of 50%, and a clock of 1/96kHz.
It is alternately switched to the L side and Ryu every cycle of z.

The digital audio signal DSa output from the changeover switch 13 is supplied to the compression circuit 14, where it is converted from a 1 sample / O bit signal to a / sample / 8 bit signal.

The digital audio signal DSa' converted into an 8-bit signal by the compression circuit 14 is supplied to a mixing means (adder) 20 constituting a mixing/separating means 86 and mixed with a digital video signal DSv, which will be described later.

The mixed digital signal DS (shown in the second diagram) is then supplied to the digital out processing circuit 22,
It is converted into a digital signal in a form compliant with the AT audio format.

As is well known, the digital out processing circuit #i22 is provided with a pit clock B Ci (clock generating means for generation, etc.).

The formatted digital signal DS is finally supplied to a rotating magnetic head (not shown) of the DAT via the digital out terminal 24 and recorded thereon.

The digital signal DS reproduced from the rotating magnetic head is supplied to a digital-in processing circuit 34 via a digital-in terminal 32 and subjected to digital-in processing. For example, a PLL circuit (not shown) is driven to generate a master clock synchronized with the reproduced pit clock BCK.

Based on this master clock, a minute H signal for separating the digital audio signal DSa and the digital video signal DSv is generated, and the next-stage separation means 36 outputs the digital audio signal DSa' (shown in FIG. 2B). A digital video signal DSv (shown in C of the same figure) is separated and output.

The 8-bit digital audio signal DSa' separated into mu units of 1/96 kHz by the separation means 36 is supplied to an expansion circuit 38. In this expansion circuit 38,
The digital audio signal DSa, which has been made into a 10-bit signal by the decompression circuit 38, undergoes processing opposite to that of the compression circuit 14, and the 1-sample 8-bit signal is returned to the 1-sample 10-bit signal. 39 movable terminals. The changeover switch 39 is supplied with a clock LRCK, and is alternately switched to the L side and R111 every 1/96 kHz.

In other words, left and right channel digital audio DSaL and DSaR are obtained at the L side and R@ fixed terminals of the changeover switch 39, respectively, with a cycle of 1/48 kHz.

The digital audio DSaL and DSaR output from the changeover switch 39 are D/input conversion@40L, 40
R and is converted into an analog signal.

An audio sampling clock fs is supplied to the A/D converters 4OL and 4OR.

The audio signals S aL and S aR output from the D/A converters 40L and 4OR are passed through a low-pass filter 41.
L, 41R are band limited and noise reduction circuit 4
After the noise is removed by 2L and 42R, it is further amplified by amplifiers 43L and 43R and sent to audio output terminal 4.
Output to 4L and 44R.

Next, a signal processing system for video signals will be explained.

The still image video signal Sν supplied to the video in terminal 50 is amplified by an amplifier 52 and then sent to an A/D converter 5.
4, and one sample is converted into an 8-bit digital signal. This A/D converter 54 has 4 f sc
(f sc is the subcarrier frequency, 3.58M
Hz) sampling clock is used.

The digital video signal DSv output from the A/D converter 54 is supplied to a fixed terminal on the a side of a changeover switch 56 that switches between an input signal and a reproduction signal. The output signal of this changeover switch 66 is supplied as a write signal to memories 62 and 64 constituting the memory means 60.

The memories 62 and 64 each have a storage capacity for one frame. Writing and reading of these memories 62 and 64 are controlled by supplying control signals to memory control circuits 70 and 72 from a controller 100 having a CPU.

The video signal Sv supplied to the terminal 50 is supplied to the subcarrier extraction circuit 110 via the amplifier 52, and the subcarrier fsc extracted by this extraction circuit 110 is supplied to the controller 100. Further, the digital video signal DSν output from the A/D converter 54 is supplied to a vertical synchronization separation circuit 112, and the vertical synchronization signal separated by this separation circuit 112 is supplied to the controller 100. Control signals are supplied to the memory control circuits 70 and 72 based on the subcarrier fsc, the vertical synchronization signal, and the bit clock BCK.

In this case, during recording, writing to the memories 62 and 64 is performed with a clock of 4 fsc, and reading is performed to one memory with a clock of 2 fsc, and reading to the other memory is performed with a clock of 2 fsc.・This is done with a clock of 4 fsc. In other words,
One memory combines the digital video signal DSv with the above-mentioned digital audio signal DSa;
It functions as a time axis compression means for the digital video signal DSv.

Also, during playback, writing to the memories 62 and 64 is performed using a clock with a frequency of 2fs, and
The reading is performed with a clock of 4 f sc. In other words, the memories 62 and 64 function as time axis expansion means for the digital video signal DSv.

The signal read from the memory 62 is transferred to the selector switch 66.
．． A signal supplied to the fixed terminal on the e side of the switch 68 and read out from the memory 64 is supplied to the fixed terminal on the f side of the changeover switch 66 and 68. Switching of these changeover switches 66 and 68 is controlled by a controller 100.

The digital video signal DSv output from the changeover switch 68 is supplied to a sync bit shift encoder 76, where a sync bit shift process is performed.

Originally, a video signal is A/D converted into 8 bits, so its sync bits are digital data in which all bits are "0". However, as described above, while the identification code ID is applied to bits that do not affect the image, the encoder 76 shifts the sync bit by one bit so that the identification code ID and the sync bit can be distinguished. (See Figure 4).

The digital video signal DSv on which the sync bits have been shifted by the encoder 76 is supplied to the adder 78, and an identification code ID is added in addition W78 (see FIG. 3). 80 is an identification code ID generator.

The digital video signal DSv to which the identification code ID has been added by the adder 78 is subjected to parallel-to-serial conversion processing in the signal processing circuit 82, and bit inversion processing is performed on the most significant bit MSB of the digital video signal DSv. This process will be described later.

After completing the predetermined signal processing in the signal processing circuit 82, the digital video signal DSv is mixed with the digital audio signal DSa' in the mixing means 20 as shown in the second diagram and sent to DATIIJ.

Furthermore, when reproducing the digital signal DS, the separating means 36
The digital video signal DSv separated is subjected to serial/parallel conversion processing in a signal processing circuit 90, and at the same time, the most significant bit MSB of the digital video signal DSv is inverted.

Then, the sync bit shift decoder 92 shifts only the sync bits in the opposite manner to the recording process, and returns them to the original sync bits (see FIG. 4).
is supplied to the fixed terminal on the h side.

Switching of the changeover switch 56 is controlled by a controller (f-controller 100), and is connected to the g side during recording, and connected to the b-side during playback.

Further, the digital video signal DSv output from the changeover switch 66 is supplied to the fixed terminal on the g side of the changeover switch 102, and the fixed terminal on the h side is connected to the A/D converter 54.
output signal is provided. Switching of the second changeover switch 102 is controlled by the controller 100. In other words, when displaying a moving image (through image) during recording, h
When displaying a still image to be recorded, it is connected to the g side. During playback, it remains connected to the g side.

The digital video signal DSv output from the changeover switch 102 is converted into an analog signal by the D/A converter 104, and then sent to the video out terminal 1 via the amplifier 106.
Output on day 0. On this terminal 10th, monitor means (
0) (not shown) is connected.

Further, the output signal of the signal processing circuit 90 is supplied to an identification code detector 94. The identification code ID detected by the detector 94 is supplied to the controller 100. Based on this identification code ID, the memory control circuit 70.72
is controlled.

During playback, when the digital video signal DSv to which the identification code ID has been added is played back and stored in the memory means 60, only image data is stored. At that time, in both odd and even fields, the final data is when a predetermined period of time has elapsed from the first data of the image data.
In order to detect this final data more accurately, in addition to management based on time, stop coat E-ID is detected, and when both match, it is determined as final image data.

Then, when the writing of the final image data of the even field is completed, the writing and reading modes of the memories 62 and 64 are reversed, and the changeover switch 66.6 is also switched to the opposite side.

By the way, during the reproduction of the digital video signal DSv, the DA
When the reproduction of T is stopped, all bits of the reproduced output data supplied to the terminal 32 become "o" as shown in FIG.

Time management (count-up processing) for image data is performed by the signal processing device shown in Figure 1.
Even if the reproduction of T is stopped, the count-up process does not stop in conjunction with this.

Therefore, one memory 64 of the memory means 60, for example, remains in the writing state, and data with all hits "0" is written as original image data. When the predetermined time closes from the DAT stop motor,
As soon as the reproduction time of the final image data of the even field arrives, all bits of the reproduction data at that time are always "0".
Therefore, this is mistakenly judged to be stop coat E-ID. As a result, the signal processing device assumes that the final image data has arrived, and switches the changeover switch 66 to
．． 68 is switched and the memory 64 is controlled to read mode.

Then, after DAT goes into stop mode, memory 6
Since all the bits "0" data written in 4 is read out and displayed as a black image, a very unsightly image will be displayed on the monitor.

To avoid this, if the most significant bit of the image data is inverted and recorded as described above and then inverted again during playback, as shown in Figure 5, the playback output data when stopped midway will be
Even if it is "0", if the re-inversion process is performed, the most significant hit MSB becomes "1".

As a result, the signal processing device side does not mistakenly judge that the final screen data has arrived, and the memory means 60 does not perform switching control, so that the previous screen is always monitored, and the above-mentioned drawbacks are eliminated. Ru.

The controller 100 also includes a shutter switch 5.
w5u, record switch 5WRE, playback switch 5W
PL, pause switch 5WPA, stop switch 5WST
and a recording mode selection switch SWMO are connected.

When the playback switch 5WPL is turned on, it is the time of playback. As a result, the DAT is placed in a playback state, and
The changeover switch 56 is connected to the b side.

The reproduced digital video signal DSv is written into one of the memories 62 and 64 via the changeover switch 56 with a clock of 2 fs. While being written into one of the memories 62 and 64, the digital video signal DSν for one frame is repeatedly read out from the other memory with a clock of 4 fsc, and the changeover switches 66 and 10
2 and is supplied to the D/A converter 104 where it is converted into an analog signal, and then supplied to a monitor to display a still image.

When one field's worth of final image data is written into one memory, the write and read modes of the memories 62 and 64 are reversed, and the selector switch 66 is also switched.

As a result, the reproduced digital video signal DSv is now written to the other memory with a clock of 2 fs, and the digital video signal DSv for one frame is repeatedly read out from the one memory with a clock of 4 f sc. , the resulting still image is displayed on the monitor.

Thereafter, reading and writing to and from the memories 62 and 64 are repeated as described above.

Next, when the recording switch 5WRE is turned on, it is time for recording. As a result, DA and T are placed in the recording state, and the changeover switch 56 is connected to allllll.

During this recording, the mote selection switch sWMO is
When connected to the S side, m1Pl and afPV, respectively, they become a one-shot mote, a manual mote and an auto mote.

In one shot mode, shutter switch 5WSH
By turning on, the image data for one frame is loaded into the memory, and this image data is recorded only once.
Automatically enters recording pause state.

In manual mode, by turning on the shutter switch 5WSH, image data for one frame is captured into the memory, and this image data is recorded one or more times.

The same image data is recorded any number of times until the recording pause state or body stop state is reached.

Automote automatically turns on the shutter, captures one frame worth of image data into memory, and records this image data. When recording is finished, the shutter is automatically turned on again, one frame worth of image data is captured in the memory, and this image data is recorded. This is repeated until the recording pause state or stop state is reached.

Next, details of the recording operation will be explained using the flowchart of FIG. 6.

When the recording switch 5WRE is turned on, step 101
recording pause is automatically turned on.

At this time, the changeover switch 56 is connected to the a side, and the A/D
The digital video signal DSv from the converter 54 is transferred to the memory 62.6 of the memory means 60 via the changeover switch 56.
4 as a write signal. Also, at this time, the changeover switch 102 is connected to the A/D converter 54.
The digital video signal DSv from the selector switch 10
A monitor (not shown) that is supplied to the D/A converter 104 via 2 and connected to the video out terminal 108 includes:
A moving image (through image) based on the video signal SV supplied to the video-in terminal 50 is displayed.

Next, in step 102, it is determined whether the mode is one-shot mode.

When the mode selection switch SWMO is connected to the S side and the mode is one-shot mode, it is determined in step 103 whether or not the shutter switch 5WS)I is on. Although not mentioned above, it is assumed that the shutter switch 5WS)I automatically returns to OFF.

When the shutter switch 5WS)1 is on in step 103, video data DSv for I frame is written to the memory 62, 64 with a clock of 4 fsc in step 104.

Next, in step 105, video data DSv for one frame is repeatedly read out from the memory 62 with a clock of 4 fSC. At this time, the changeover switch 102 is switched from the h side to glN, so the video data DSv for one frame read from the memory 62 is supplied to the D/A converter 104 via the changeover switch 66.102. A still image is displayed on the monitor connected to terminal 10.

Next, in step 106, it is determined whether the pause switch swPA is off. When it is not off, the process returns to step 103; when it is off, the process returns to step 10.
7, video data DSv for one frame is read out from the memory 64 with a clock of 2 fs, and this is mixed with the digital audio signal DSa' as described above through the changeover switch 68 and recorded as DAT. .

Next, in step 10, it is determined whether the recording is complete. When recording of video data DSV for one frame is completed, the recording pause is automatically turned on in step 109.

Then, in step 110, the changeover switch 102
A moving image (through image) based on the video signal Sv supplied to the video in terminal 50 is displayed on the monitor connected to the video out terminal 108, and the process returns to step 103.

Also, in step 103, the shutter switch 5WSH
When is off, it is determined in step 111 whether or not a through image is being displayed on the monitor. If a still image is displayed instead of a through image, step 105
Proceed to. When the through image is being displayed, it is determined in step 112 whether the pause switch 5WPA is off.

If it is not off, the process returns to step 103. When it is off, in step 113, a still image is displayed on the monitor in the same manner as in step 105, and the process proceeds to step 107.

Further, if it is determined in step 102 that the mode is not one-shot mode, it is determined in step 115 whether or not the manual mode is selected.

When the mode selection switch SWMO is connected to the m side and the mode is manual mode, it is determined in step 116 whether the shutter switch 5WSH is on or not.

When the shutter switch 5WSH is on, one frame worth of video data DSv is written into the memories 62 and 64 of the memory means 60 in step 117.

Next, in step 118, a still image is displayed on the monitor in the same manner as in step 105. And step 11
At step 9, it is determined whether the pause switch 5WPA is off. If it is not off, the process returns to step 116.

When it is off, do the same as step 107,
One frame worth of video data DSv is read out from the memory 64, mixed with the digital audio signal DSa', and recorded as DAT.

Next, in step 121, it is determined whether recording is complete. When recording is completed, it is determined in step 122 whether the pause switch 5WPA is on. If it is not on, the process returns to step 118. When it is on, a through image is displayed on the monitor in step 123 in the same manner as in step 110, and in step 116
Return to

If the shutter switch 5WSH is not on in step 116, it is determined in step 124 whether or not a through image is being displayed on the monitor.

If a still image is being displayed instead of a through image, the process advances to step 118. When the through image is being displayed, it is determined in step 25 whether or not the pause switch 5WPA is off. If it is not off, the process returns to step 116. When it is off, a still image is displayed on the monitor in step 126 in the same manner as in step 105, and the process proceeds to step 120.

Further, if it is determined in step 115 that the mode is not one-shot mode, it is determined in step 128 whether or not the mode is auto mode.

When the mode selection switch SWMO is connected to the a side and the mode is auto mode, it is determined in step 129 whether the pause switch 5WPA is off. When it is off, in step 130, the controller 100
After the shutter inside is turned on,
At step 31, video data DSv for one frame is written into the memories 62 and 64 of the memory means 60.

Next, in step 132, a still image is displayed on the monitor in the same manner as in step 105. And step 13
3, in the same way as step 107, 1 is read from the memory 64.
Video data DSV for one frame is read out, mixed with digital audio signal DSa', and recorded as DAT.

Next, in step 134, it is determined whether the recording is completed or not. When the recording is complete, the process returns to step 129.

Further, if it is determined in step 128 that the mode is not auto-mote, the process returns to step 102.

Note that when the recording switch 5WRE is turned on and the stop switch 5WST is turned on in any mote, the recording switch 5WRE is turned on and the stop switch 5WST is turned on by interrupt processing.

At this time, the changeover switch 102 is connected to the h side, and a through image is displayed on the monitor.

By the way, during playback, the memory 62.6 of the memory means 60
It takes about 5 seconds to write one frame worth of video data DSv to the memory card 4.

Therefore, video data DSv and audio data DSa' are recorded on the tape using DAT as shown in FIG. 7A.
If the video data DS for one frame is written in the memory 62, 64, the video data for one frame DSvli: is read out repeatedly, and a still image is displayed on the monitor. , the relationship between the reproduced sound and the reproduced image will be as shown in Figure B. In other words, the image will be displayed approximately 5 seconds after the sound is output, and the relationship between the reproduced sound and the reproduced image will be as shown in Figure B. The playback timing is significantly different from the image.

In order to improve such timing deviation, memory 6
2. When the writing of one field's worth of video data DSv is completed in 64, until the video data DSv of another one field is written, the first written one field is It is conceivable to repeatedly read out the video data DSv for 30 minutes and display a still image based on a field signal on a monitor. Although not mentioned above, in the signal processing device shown in FIG. 1 as well, a still image based on a field signal is displayed at the start of playback.

When video data DSv and audio data DSa' are recorded in association with each other as shown in FIG. 7A, the relationship between reproduced audio and reproduced image becomes as shown in FIG. 7C.

In other words, the image is displayed approximately 2.5 seconds after the audio is output, and there is still a lag in the playback timing between the audio and the image.

Therefore, in this example, as shown in FIG. 8A, for one frame of video data DSv, the corresponding audio data DSa' is recorded from the time when one field is recorded. Ru. In other words, the controller 100 outputs a synchronization signal as shown in FIG. Audio signal S aLXS
The supply timing of aR is controlled.

Note that depending on the timing of the synchronization signal, the light emitting element,
For example, the user may be informed of the timing of voice input by lighting an LED.

In this example, the recording timings of the video data DSV and the audio data DSa' are shifted by about one field interval, so the relationship between the reproduced image and the reproduced audio becomes as shown in Figure C. , the playback timings of the image and audio will match.

By the way, in the DAT, the program number for search is recorded in the sub-coat area of the track format (shown in FIG. 9).

The scanning locus of the head during the search (FF search, REW search) spans several tracks, as shown by solid line arrows in FIGS. 10A and 10B. Therefore, for example, when searching 200 times, the probability that the head will pass through the subcourt area is 9.
That's no more than three times per second (the recording time of the same program number on the current DAT).

Taking into account that the sub-code can be read without error using a 200x search, it is difficult to shorten the recording time of 9 seconds.

On the other hand, as mentioned above, the video data DS for one frame
v is recorded as approximately 5 seconds or υ) in DAT. Therefore, if a program number is assigned corresponding to approximately 5 seconds in which video data DSv for each frame is recorded, 20
A 0x search becomes impossible.

Furthermore, if a program number is assigned every 5 seconds, a 2-hour DAT tape will require 1400 or more program numbers.

Therefore, a program number is assigned corresponding to about 5 seconds in which a portion of the video data DSv is recorded for each frame, and in addition to the areas of program numbers 1 to 3,
Add a 4-digit program number using half of the index number area (see pack format in Figure 11).

When a 4-digit program number is attached every approximately 5 seconds, the upper 3 digits of the 4-digit program number are approximately 5C1 leapt. D.A.
The search in T is performed using this fact.

FIG. 12 shows the configuration of the parts involved in the DAT search.

In the figure, a reproduced signal from the head is supplied to a subcode processing circuit 201, and this subcoat processing circuit 201
The program number data DPR from is supplied to the CPU 202.

Further, 204 is a capstan motor, and a frequency signal SFG from a frequency generator FG attached to this motor 204 is supplied to a capstan control circuit 203. This control circuit 203 controls the rotation speed and rotation direction of the motor 204. The operation of the control circuit 203 is based on the program number data DPR.
202.

When searching for a certain 4-digit program number,
Utilizing the fact that the upper three digits of the four-digit program number remain the same for about 50 seconds, the upper three digits are searched by a 200x search. In other words, the sub coat processing circuit 201
Until the upper three digits of the block number indicated by the data DPR supplied to the CPU 202 match the target value,
A 200x search is performed.

Next, when the top three digits match the target value, the CPU2
The control circuit 203 is controlled by 02, and a 16 times search is performed. That is, the 16x search is performed until all digits of the program number indicated by the data DPR match the target value.

Figure 13 shows the operation when searching for program number 1254, in which a 200x search (high speed search) searches for parts 1250 to 1259, and then a 16x search (low speed search) searches for 1254. part is searched.

Note that the 200x and 16x searches are just examples, and the speed is not limited to these as long as the speed is such that the upper three digits and all digits of the program number can be read, respectively.

By the way, by using the signal processing device shown in the example in FIG. 1, it is possible to perform digital dubbing using two DATs on a tape in which a digital audio signal DSa and a digital video signal DSν are mixed and recorded on a DAT. , the lower 8 bits of the digital video signal D
It is conceivable that Sv is recorded as is, and the upper 8 bits of the digital audio signal DSa' are replaced with other contents.

FIG. 14 shows a configuration for digital dubbing using two DATs.

In the same figure, 301 is the DAT on the master side, and 301 is the DAT on the master side.
02 is a DAT on the slave side. The digital signal DSm (shown in FIG. 16A, see the second diagram) output from the DAT 301 is sent to
The signal is supplied to the AT 302 as a recording signal, and is also supplied to the DAT 302 as a recording signal via the b side of the changeover switch 303 and the dubbing device 304.

In addition, the pit clock BC output from DAT301
K (shown in FIG. 16C) and a clock LRCK for switching between left and right channels (shown in FIG. 16B) are supplied to the DAT 302 and the post-recording device 304 as synchronization reference signals.

Further, the audio signals S al and S sR of the left and right channels are supplied to the dubbing device 304 .

FIG. 15 is a diagram showing a specific configuration of the post-recording device 304.

In the figure, the digital signal DSm supplied from the DAT 301 via the changeover switch 303 is supplied to the & sword fixed terminal of the changeover switch 341.

Clock BCK and LRCK from DAT 301 are supplied to timing generation circuit 343.

In addition, the left and right channel audio signals S am and SaR
is supplied to the signal processing circuit 342. This signal processing circuit 342 is supplied with a clock LRCK, and is also supplied with a clock having a frequency fs from a timing generation circuit 343.

This signal processing circuit 342 is the amplifier 9L in FIG.
, 9R to compression circuit 14, and outputs an 8-bit compressed digital audio signal DSa' (shown in FIG. 16, see FIG. 2B). This digital audio signal DSa' is transferred to the selector switch 34.
It is supplied to the fixed terminal on the b side of 1.

Furthermore, the timing generation circuit 343 uses a clock BCK.
, LRCK, the digital signal DSm becomes a low level "0" in response to the video signal DSv, and becomes a high level "1°" in response to the audio signal DSa, and the state changes every 8 bit clocks. A clock WCK (shown in FIG. 16 ε) is generated.

The word clock WCK is supplied to the changeover switch 341 as a changeover control signal. The changeover switch 341 is connected to the a side when the clock WCK is at a low level "0'°," and is connected to the b side when the clock WCK is at a high level i+1++.

As a result, the changeover switch 341 outputs a digital signal DSs (shown in FIG. 16F) in which the audio signal DSa' portion of the digital signal DSm is replaced, and this digital signal DSs
04 output signal.

Returning to FIG. 14, when dubbing, the selector switch 303
When connecting the DAT 301 to the a side, the digital signal DSm output from the DAT 301 is directly supplied to the DAT 302 and recorded.

Furthermore, when the changeover switch 303 is connected to the b side during dubbing, the digital signal DSs output from the dubbing device 304 is supplied to the DAT 302 and recorded. In other words, audio dubbing processing is performed.

In the above embodiment, the tape speed was increased by 200 times,
Although the search is performed by controlling the program number in two stages, the search may be performed in more stages depending on the number of digits of the program number.

Furthermore, in the above embodiment, for the total number of bits of 16, the audio signal DSa' is the upper 8 bits of the video signal D.
Although Sv is allocated to the lower 8 bits for recording and reproduction, it goes without saying that the number of bits and the allocation position are not limited thereto.

Further, in the above embodiment, the audio signal is compressed and recorded, but the present invention can also be applied to the audio signal recorded without being compressed.

Further, in the above-described embodiments, a magnetic recording and reproducing device was shown, but an optical recording and reproducing device may be used.

[Effects of the Invention] As explained above, according to the present invention, the search is not performed by reading all digits of the program number from the beginning, but by gradually reducing the tape speed and reading from the upper digits. By doing this, it is possible to perform an accurate search without increasing the search speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal processing device, FIG. 2 is a diagram showing an example of the format of a digital signal, FIG. 3 is a diagram showing the structure of recording data, and FIG. 4 is an explanatory diagram of sync bit shift processing. Fig. 5 is an explanatory diagram of the most significant bit inversion, Fig. 6 is a flowchart showing the recording operation, Figs. 7 and 8 are explanatory diagrams of the reproduction timing of images and audio, and Figs. 9 to 13.
The figure is a diagram for explaining the search, and FIGS. 14 to 16 are diagrams for explaining the audio dubbing. 14th issue 36 ・ 38th issue 62.64 ◆ 80 ・ ・Compression circuit・Mixing means・Separation means・Expansion circuit・Memory means・Identification code generator 94...Identification code detector 201...Sub-coat processing circuit 202...・CPU 203... Capstan control circuit 204... Capstan motor 301, 302... DAT 304... Track format of dubbing device DAT Figure 9 Head quantification of search engine Figure 10 Dimensions 7- Fig. 11 DA"rr)" 7-chi 1 = IVIT Partial dubbing equipment configuration diagram Fig. 15

Claims (1)

[Claims] (1) An N-bit (N is an integer) digital audio signal and an M-bit (M is an integer) digital video signal are combined and recorded on tape as an N+M-bit digital signal, and one screen of the above digital video signal is recorded. A multi-digit program number is recorded on the tape each time, a target program number is given, and when searching for that position on the tape, the tape speed is gradually reduced to a speed that allows reading up to the upper predetermined digits of the program number. A search method characterized by performing a search by