JPH0447869A - fade processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is used in video editing machines, etc., to gradually increase or decrease the level of video signals, etc., and to fade in/fade out ( fade in
The present invention relates to a fade processing device that performs a gradual increase or decrease using digital processing.

[Prior Art] Conventionally, this type of fade processing device, for example, in the case of an analog type, inputs a video signal etc. to a sliding variable resistor (attenuator) and changes the value of the variable resistor. In other words, by controlling the gain from 0% to 100%, the levels of these signals are changed and the signals are mixed.

Fade-in and fade-out by the fade processing device uses a sliding variable resistor, which can be done at low cost, but the variable resistance value must be changed manually, in other words, by manual operation.

[Problems to be Solved by the Invention] By the way, video editing machines and the like are increasingly being digitized, and the control of the fade processing device described above is also being performed digitally, but noise is generated due to the digitization. In order to prevent the influence of noise, for example, various precautions must be taken in designing.

This invention was made in view of the above-mentioned problems, and its purpose is to provide an inexpensive fade processing device that can perform fade-in/fade-out of video signals by digital processing, without having to consider the influence of noise. Our goal is to provide the following.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a fade processing device that gradually increases or decreases the level of a video signal and enables fade-in and fade-out of the video. first and second memories capable of alternately writing data that gradually increases or decreases corresponding to the number of bits of digital video data such as the video signal, and the data that gradually increases or decreases gradually; first and second buffers for alternately writing data into the first and second memories, and data gradually increased or decreased through the first or second buffers, and a microcomputer that writes data alternately into the memory of the microcomputer, first and second selectors that switch the address and input video data from the microcomputer every V synchronization of the video signal, and output data of the first memory and the second selector. The memory output data and the above ■
and a third selector which is switched every synchronization, and alternately writes the gradually increased or decreased data into the first and second memories using the address from the microcomputer, and writes the digital video data into the first memory using the address from the microcomputer. The gist of the present invention is to alternately read data from the second memory and the second memory, and output the read data as video data.

[Function] With the above configuration, the first and second selector sections are switched every time the video signal is V synchronized. For example, when the first selector section is switched to the microcomputer side, the second selector section is switched to the microcomputer side. section is switched to the digital video data side. In this way, the first selector section and the second selector section are always switched in the opposite direction, so that, for example, in the case of a fade-in, gradually increasing data from the microcomputer is stored in the first and second memories at every V synchronization. written alternately. Then, when gradually increasing data is written to the first memory, the video data becomes the address of the second memory, so the data of the second memory (the data written last time) is written to the third selector section. It is output as video data via .

Subsequently, in the next V synchronization, when gradually increasing data from the microcomputer is written to the second memory, the video data becomes the address of the first memory, so the data of the first memory (previous (written data) is output as video data via the third selector section.

In this way, data that is gradually increasing is output as video data every synchronization.

The fade-in of the video signal can be performed by digital processing. Furthermore, in the case of fade-out, data that gradually decreases may be written alternately into the first and second memories every V synchronization.

[Example] Hereinafter, an example of the present invention will be described based on FIGS. 1 to 3.

In FIG. 1, the fade processing device has first and second memories that alternately write data that gradually increases or decreases digital video data such as a video signal, and reads the data using the digital video data as an address. (RAM backup tables) 1 and 2, and first and second buffer sections 3 and 4 for alternately writing the above-mentioned gradually increasing or gradually decreasing data into the first and second memories 1 and 2. and a microcomputer 5 that performs control to alternately write the gradually increasing or gradually decreasing data into the first or second memory 1 or 2 via the first or second buffer section 3 or 4; First and second selector sections 6 switch between the address from the microcomputer 5 and the digital video data and output the same to the first or second memory 1 or 2.
,7.

A third selector section 8 is provided that outputs data alternately read from the first and second memories.

Next, the operation of the fade processing device having the above configuration will be explained with reference to the second time chart and the schematic diagram of the memory shown in FIG.

First, a video signal, etc. is converted into digital data, and digital video data is obtained.
n) It is assumed that an instruction to do so has been input.

Then, the microcomputer 5 performs control to alternately write data that is gradually increasing or decreasing in the first and second memories 1 and 2 for the purpose of the fade-in.

At this time, the first selector section 6 is switched to the A side (second
(shown in FIG. 2(b)) and is switched to the second selector unit 7 (shown in FIG. 2(c)), the address from the microcomputer 5 is designated as the first memory 1, and the first
The buffer section 3 of is turned on. Therefore, the microcomputer 5 uses the address (00, 01, 02,...
・, FE.

FF) and the first data (shown at the right end in Figure 3; 00,0
0°00, ..., oo, oo) is the first buffer section 3
(as shown in FIG. 2(e)). Then, at the next V synchronization, the second selector section 7 is switched to the A side, and the first selector section 7 is written to the A side. 6 is switched to the B side, the address from the microcomputer becomes the address specification for the second memory 2, and the digital video data becomes the address specification for the first memory 1.

Therefore, the address (00
, 01, 02, ..., FE, FF), which has increased from the previous data (for example, oo, oo, oo).

. . , 01, 01, 02) are written into the second memory 2 via the second buffer unit 4 (as shown in FIG. 2(f)).

Thereafter, in the same manner, the first selector section 6 and the second selector section 7 are alternately switched to the A side every time V synchronization of the video signal, etc. is performed, so that as shown from the right end to the left end in FIG. , gradually increasing data is alternately written into the first and second memories 1 and 2.

On the other hand, when the first selector section 6 is switched to the A side, that is, when gradually increasing data is being written to the first memory 1, the second selector section 6 is switched to the B side, so that the input The digital video data is addressed to the second memory 2 via the second selector section 7. Therefore, when the data shown in the center of FIG. 3 is written in the second memory 2, if the input digital video data is (03), (00) is read out, and the video data becomes (FC). Then, (7C) will be read. Furthermore, when the second selector section 7 is switched to the A side, that is, when gradually increasing data is being written to the second memory 2, the first selector section 6 is switched to the B side. , input digital video data is addressed to the first memory 1 via the first selector section 6. Therefore, when the data shown at the left end of FIG. 3 is written in the first memory 1, if the muca digital video data is (03), then (0
3) is read out and the image (FC) is (F
C) is read out.

Subsequently, as shown in FIG. 2(d), in the third selector section 8, due to the synchronization of the video signal,
When the data in the first memory 1 is being read, that is, when gradually increasing data is being written into the second memory 2, the switch is switched to the A side, and when the opposite is the case, the switch is switched to the B side. Therefore, data (gradually increasing data) alternately written in the first and second memories 1 and 2 is outputted as digital video data via the third selector section 8.

In this way, in the case of a fade-in operation, the first and second
Gradually increasing data is alternately written into the memories 1 and 2 of the first and second memories 1 and 3, in other words, the data in the first and second memories 1 and 3 is updated with the gradually increasing data so that it approaches the input digital video data. Fade-in is possible by using the first and second memories 1 and 2 as look-up tables and using the input digital video data as the address from which data in these tables is read.

Note that although the above embodiments have been described with respect to the fade-in operation, the same applies to the case of the fade-out operation. In this case, as shown from the left end to the right end in FIG. 3, the data alternately written into the first and second memories 1 and 2 gradually decreases.

In addition, since the data in the first and second memories 1 and 2 are rewritten, when the data is updated differently, for example, when the image is brightened or made pure white (all data is "FF"), the image is It is possible to obtain various effects such as switching and returning the video data to the original state.

[Effects of the Invention] As explained above, according to the fade processing device of the present invention, depending on the number of bits of digital video data,
Data that gradually increases or decreases during synchronization is the first
and the second memory alternately, the first and second memories are used as lookup tables, and the digital video data is used as the address of the table. By alternately writing to the first and second memories, a fade-in operation is possible, and conversely, by alternately writing data that is gradually decreasing in V synchronization to the first and second memories, a fade-out operation is possible. In/out can be performed digitally, which has the advantage of not being affected by noise.

[Brief explanation of drawings]

Fig. 1 is a schematic block diagram of a fade processing device showing an embodiment of the present invention, Fig. 2 is a time chart diagram for explaining the operation of the above fade processing device, and Fig. 3 is a schematic block diagram of a fade processing device used in the above fade processing device. FIG. In the figure, 1 is a first memory section (RAM), 2 is a second memory section (RAM), 3 is a first buffer section, 4 is a second buffer section, 5 is a microcomputer, and 6 is a first memory section. , 7 is a second selector section, and 8 is a third selector section. Patent Applicant: Fujitsu General Co., Ltd. Agent, Patent Attorney: Takuya Ohara Procedural Amendment (Spontaneous) 1゜Indication of the Case 1990 Patent Application No. 156790 2゜Name of the Invention Fade Processing Device 4゜5゜

Claims (1)

[Claims] (1) In a fade processing device that gradually increases or decreases the level of a video signal and makes it possible to fade in and fade out the video, the level of the video signal increases gradually in accordance with the number of bits of digital video data such as the video signal. , or first and second memories to which gradually decreasing data can be written alternately; and a first memory to alternately write gradually increasing data or gradually decreasing data to the first and second memories. and a second buffer, a microcomputer that alternately writes data that is gradually increased and decreased or gradually decreased through the first or second buffer into the first and second memories, and addresses and input images from the microcomputer. first and second selectors that switch between the data and the video signal every V synchronization; and a third selector that switches between the output data of the first memory, the output data of the second memory, and the V synchronization. , writing the gradually increased or gradually decreased data into the first and second memories alternately using the address from the microcomputer, and alternately reading the data in the first and second memories using the digital video data as the address; A fade processing device characterized in that the read data is output as video data.