JPH0448821A - logic circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution and to reduce the number of circuit components by using a diode provided in parallel with a collector load of an input transistor(TR) of a phase split circuit for a clamp circuit limiting the low level of an output signal of an SPL circuit. CONSTITUTION:A diode D1 is provided in parallel with a MOSFETQ1 being a collector load between the ground level of the logic circuit and the collector of an input TR T1. The diode D1 has a forward voltage equivalent to the base-emitter voltage VBE of an NPN bipolar TR. Thus, when the output signal SO of an SPL circuit is going rapidly to go to a low level such as the power supply voltage of the logic circuit, the low level of an inverted output signal of a phase split circuit is clamped at the level of almost -VBE. Furthermore, the low level of the output signal SO is clamped at the level of almost -2XVBE. Thus, while the circuit constitution of the SPL circuit is simplified, the clamp effect onto the output signal SO is enhanced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to logic circuits, and includes, for example, SPLs installed in high-speed logic integrated circuit devices such as high-speed combinators.
(Super Pu5h-pull Logic)
It relates to techniques that are particularly effective when used in circuits.

[Prior Art] NTL (Non Threshold Logic) includes a phase division circuit that receives an input signal and an output limiter follower circuit that transmits an inverted output signal of the phase division circuit.
c) There is a circuit. There is also a so-called SPL circuit in which the output section of the NTL circuit is replaced with an active pull-down circuit.

Regarding SPL circuits, for example, Japanese Patent Application Laid-Open No. 1-26102
It is described in Publication No. 4, etc.

[Problem to be solved by the invention]

Prior to the present invention, the inventors of the present application developed an SPL circuit as shown in FIG. 4, which was made by adding several improvements to the conventional SPL circuit as described above. That is, in FIG. 4, the 5PLl path is a P-channel MO5FETQI for speeding up the rise of the inverted output signal of the phase division circuit, that is, the collector potential of the input transistor TI.
and diodes D4 and D5 for clamping the output signal SO and suppressing its undershade noise.The SPL circuit also includes a resistor R2 and diodes D2 and D3, and a predetermined bias voltage is applied to the bias transistor T2. As a result, the SPL
The circuit operation becomes faster and more stable.

However, the inventors of the present application have found that the SPL circuit shown in FIG. 4 still has the following problems. That is, in the SPL circuit shown in FIG. 4 above,
In order to take various measures, the number of circuit elements in the SPL circuit has increased, and this is one of the factors that hinders the cost reduction of high-speed logic integrated circuit devices and the like.

An object of the present invention is to provide an SPL circuit with a simplified circuit configuration and a reduced number of circuit elements. Another object of the present invention is to reduce the number of circuit elements in a high-speed logic integrated circuit device or the like constructed based on an SPL circuit, thereby promoting cost reduction.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a clamp circuit that limits the low level of the output signal of the SPL circuit is configured by one diode provided in parallel with the collector load of the input transistor of the phase division circuit.

[For production]

According to the above-mentioned means, the circuit configuration of the 5 PLU path can be simplified and the number of circuit elements can be reduced while enhancing the Kranob effect on the output signal. As a result, it is possible to reduce the number of circuit elements such as a high-speed logic S8 circuit device configured based on an SPL circuit, and to promote cost reduction.

[Embodiment] FIG. 1 shows a circuit diagram of an embodiment of an SPL circuit to which the present invention is applied. Based on the figure, an overview of the configuration and operation of the SPL circuit of this embodiment and its characteristics will be explained.

Note that the SPL circuit of this embodiment is installed in a high-speed logic integrated circuit device such as a high-speed computer together with a large number of similar SPL circuits, although this is not particularly limited. gJIFy
Although not particularly limited, each circuit element of J is formed on a single semiconductor substrate such as single crystal silicon along with other circuit elements constituting a high-speed logic integrated circuit device.

In the circuit diagrams below, the MOSFETs (metal oxide semiconductor field effect transistors, in this specification, MOSFETs are collectively referred to as insulated gate field effect transistors) are not particularly limited, but are all P
It is a channel MO3FET, and the illustrated transistors (in this specification, bipolar transistors are simply referred to as transistors) are NPN type transistors.

In FIG. 1, the SPL circuit of this embodiment includes, but is not limited to, an input transistor Tl that receives a predetermined input signal Sl at its base.
Although the collector of I is not particularly limited, the collector of P channel M
It is coupled to the circuit's ground potential (first power supply voltage) via an O3FET QI (load means), and its emitter is coupled to the circuit's power supply voltage (second power supply voltage) via an emitter resistor R1. These input transistor T1, MO3FET QI, and resistor R1 constitute a phase dividing circuit, that is, an input inverting section of the SPL circuit. Here, the power supply voltage of the circuit is not particularly limited, but for example -2, O
It is assumed to be a negative power supply voltage such as v. In addition, the input signal Sl
is a relatively small amplitude digital signal having, for example, a high level of 10.8V and a low level of -1.4V, although there are no particular restrictions thereon.

Although not particularly limited, an input signal S■ is supplied to the gate of MO5FETQI constituting the phase division circuit. As a result, when the input signal Sl is at a low level and the input transistor Tl is turned off, the MO5FETQI is selectively turned on, and the input transistor T
It has the effect of rapidly charging the parasitic capacitance coupled to the collector node of I, thereby speeding up the rise change of the output signal SO of the circuit.

In this embodiment, between the ground potential of the circuit and the collector of the input transistor TI, there is a MO
One diode D1 is provided in parallel with 5FETQI. This diode DI is assumed to have a forward voltage equivalent to the base-emitter voltage VBH of an NPN bipolar transistor, although it is not particularly limited.
As will be described later, it acts as a clamp circuit that clamps the low level of the output signal SO of the SPL circuit at a level of approximately -2XVBH.

The SPL circuit further includes a pair of output transistors T3 (first output transistor) and T4 (second output transistor) arranged in totem pole configuration between the circuit's ground potential and power supply voltage.

Among these, the base of the output transistor T3 is connected to the inverted output node of the phase division circuit, that is, the input transistor T3.
1, and the base of the output transistor T4 is coupled via a capacitor C1 to the non-inverting output node of the phase divider circuit, ie the emitter of the input transistor Tl. A resistor R4, which together with the capacitor C1 constitutes a differential circuit, is provided between the base of the output transistor T4 and the power supply voltage of the circuit. Also, the commonly coupled emitters and collectors of output transistors T3 and T4 are coupled to the output terminal SO of the SPL circuit. As a result, the output transistors T3 and T4 constitute a so-called push-pull output circuit, and the differential circuit consisting of the output transistor T4, capacitor C1, and resistor R4 is
It acts as an active pull-down circuit for the other output transistor T3.

Although not particularly limited, a bias transistor T2 is provided between the ground potential of the circuit and the base of the output transistor T4. A predetermined bias voltage higher than the power supply voltage of the circuit by 2XV8E is applied to the base of the transistor T2 from a voltage generating circuit consisting of a resistor R2 and diodes D2 and D3 via a base resistor R3. As a result, a bias voltage higher than the power supply voltage of the circuit by VBE is applied to the output transistor T4.

As a result, output transistor T4 is biased to the state just before it turns on.

The base of the bias transistor T2 is coupled to the output terminal SO of the SPL circuit via a capacitor C2, although this is not particularly limited. This capacitor C2 constitutes a feedback circuit that transmits the level change of the output signal SO to the base of the output transistor T4, thereby
The falling change of is accelerated.

When the input signal Sl is set to high level, the input transistor Tl is turned on in the phase division circuit, and MO5
FETQI is turned off. Therefore, the inverted output signal of the phase division circuit, that is, the collector potential of the input transistor Tl, becomes a predetermined low level, and the non-inverted output signal, that is, the emitter potential of the input transistor TI, becomes a predetermined high level.

The low level of the inverted output signal of the phase dividing circuit is transmitted as is to the base of the output transistor T3, and the rising edge of the non-inverted output signal is transmitted to the capacitor C1 and the resistor R4.
The signal is transmitted to the base of the output transistor T4 via a differentiating circuit consisting of the following. Therefore, the output transistor T3 is turned off, and the output transistor T4 is temporarily turned on. As a result, the output signal so of the SPL circuit is
It rapidly tries to become a low level like the power supply voltage of a circuit. However, the ground potential of the circuit and the input transistor TI
As mentioned above, there is a diode DI between the collector of
A clamp circuit consisting of
Furthermore, the low level of the output signal SO is clamped at a level of approximately 2XVBH. This simplifies the circuit configuration of the SPL circuit while increasing the clamping effect on the output signal SO, thereby suppressing undershoot noise in the output signal SO of the SPL circuit. As a result, the operation of a high-speed logic integrated circuit device based on an SPL circuit is stabilized.

On the other hand, when the input signal S1 is set to a low level, the input transistor TI is turned off in the phase division circuit, and the MOSFET Ql is turned on instead. For this reason,
Similarly, the high level of the inverted output signal of the 0-phase sub-circuit, where the inverted output signal of the phase dividing circuit becomes a high level similar to the ground potential of the circuit, and the non-inverted output signal becomes low level, similarly, the high level of the inverted output signal of the sub-circuit is directly connected to the output transistor T3. The falling change of the non-inverted output signal is transmitted to the base of the output transistor T4 via the differentiating circuit.

As a result, the output transistor T4 is turned off, and
Instead, the output transistor T3 is turned on. As a result, the output signal SO of the SPL circuit is set to a high level such as -VBE. At this time, the diode D1 constituting the clamp circuit is connected to the MOSFE which is in the on state.
It is short-circuited by TQl and has no effect.

As described above, in the SPL circuit of this embodiment, the clamp circuit for suppressing the low level of the output signal SO is a single clamp circuit provided in parallel with the collector load of the input transistor Tl constituting the phase dividing circuit. It is composed of a diode DI. Therefore, the clamping effect on the output signal SO is enhanced, the circuit configuration of the SPL circuit is simplified, and the number of circuit elements is reduced. This makes it possible to reduce the number of circuit elements in a high-speed logic integrated circuit device based on SPL circuits, thereby promoting cost reduction.

As shown in the above embodiment, the present invention can be applied to an SPL installed in a high-speed logic integrated circuit device such as a high-speed computer.
By applying it to the circuit, the following effects can be obtained. In other words, (11) By configuring the clamp circuit that limits the low level of the output signal of the SPL circuit with one diode installed in parallel with the collector load of the input transistor of the phase division circuit, the output signal of the SPL circuit This has the effect of increasing the clamping effect on the noise and further suppressing the undershoot noise.

(1) Item (1) above provides the effect of simplifying the circuit configuration of the 5PLl path and reducing the number of circuit elements.

(3) Items (1) and (i) above have the effect of reducing the number of circuit elements in high-speed logic integrated circuit devices, etc. that are based on SPL circuits, and promoting cost reduction. It will be done.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, the SPL circuit can have any number of inputs and any logical function by changing the number and connection form of the input transistors that form the phase division circuit. In addition, the SPL circuit is
As illustrated in FIG. 2, a collector load consisting of a resistor R5 can be provided in place of the MOSFET Ql, and the third B! ! As exemplified in 1, MOSFETQ
1 and a resistor R5 may also be provided together. In each embodiment, the number of diodes constituting the clamp circuit can be changed depending on the level to be clamped, and bipolar transistors in the form of diodes, for example, can also be used instead of diodes. Furthermore, the specific circuit configuration of the SPL circuit, the polarity and absolute value of the power supply voltage, the conductivity types of the transistors and MOSFETs, etc. may be modified in various embodiments.

The above explanation has mainly been about the application of the invention made by the present inventor to the SPL circuit installed in high-speed logic integrated circuit devices, which is the field of application that formed the background of the invention, but the invention is not limited thereto. For example, the present invention can be applied to SPL circuits and similar logic circuits installed in gate array construction circuits, various dedicated logic integrated circuit devices, etc. The present invention includes at least a phase division circuit, an active pull-down circuit, and a clamp circuit. It can be widely applied to logic circuits and semiconductor integrated circuit devices equipped with such logic circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by configuring the clamp circuit that limits the low level of the output signal of the SPL circuit with one diode installed in parallel with the collector load of the input transistor of the phase division circuit, the clamping effect on the output signal of the SPL circuit can be reduced. It is possible to reduce the number of circuit elements by making the circuit configuration of the SPL circuit S-element while increasing the SPL circuit. This results in
It is possible to reduce the number of circuit elements in a high-speed logic integrated circuit device or the like configured based on an SPL circuit, thereby promoting cost reduction.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of an SPL circuit to which the present invention is applied. FIG. 2 is a circuit diagram showing a second embodiment of an SPL circuit to which this invention is applied. FIG. 3 is a circuit diagram showing a third embodiment of the SPL circuit to which the present invention is applied. ji! FIG. 4 is a circuit diagram of an SPL circuit developed by the inventors of the present invention prior to this invention. Tl~T4...NPN type bipolar transistor, Q
l...P channel MO3FETSD1~D5...
Diode, 01-c2...Capacitor, R1-R5
···resistance. 1st rIA Figure 3 Figure 21!1 Figure 4

Claims (1)

[Claims] 1. A phase dividing circuit including an input transistor having its base receiving an input signal and a load means provided between a first power supply voltage and the collector of the input transistor;
a clamp circuit provided in parallel with the load means;
a first circuit provided between the first power supply voltage and the output terminal of the circuit and receiving at its base the inverted output signal of the phase dividing circuit;
and a second output transistor that is provided between the output terminal of the circuit and a second power supply voltage and receives at its base a differential signal of the non-inverted output signal of the phase division circuit. A logic circuit that 2. Claim 1, wherein the clamp circuit is constituted by one diode.
Logic circuit described in section. 3. The logic circuit according to claim 1 or 2, wherein the logic circuit is an SPL circuit installed in a high-speed logic integrated circuit device such as a high-speed computer.