JPH0449503A - Write preshift circuit for magnetic disk device - Google Patents

Abstract

PURPOSE:To suppress the increase of the number of electronic parts and signal lines to miniaturize a circuit and of an integrated circuit by inputting the output signal of a P-channel open drain logic gate and delaying it to shape the waveform and outputting the result. CONSTITUTION:A write pulse train signal S1 is successively stored in a shift register 1 and is inputted to a pattern decoder 2. The decoder 2 outputs a distributed write pattern signal S3 and an undistributed write pattern signal S4. The signal S3 drives a P-channel open drain logic gate group 4 to turn on/off a current to the capacitor in a time delay device 5. The signal S4 drives a logic gate 3 to turn on/off the current of the circuit 5. By this operation, turning-on/off of the gate group 4 is controlled when the gate 3 is turned on, and the generated potential is inputted to a buffer logic gate 6 and has the waveform shaped and is outputted as a write preshift signal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a write preshift circuit for a magnetic disk device, and more particularly to a write preshift circuit for a magnetic disk device for adding a phase shift to a write pulse train signal. .

[Conventional technology]

A write preshift circuit of a conventional magnetic TiSF device for adding a phase shift of 1- to a write pulse train signal uses a pattern decoder to convert the storage pattern of a shift register that sequentially stores and sequentially shifts the write pulse train signal and outputs it. The write pulse train is divided into multiple groups according to the time value to be added by , a time delay device is connected to each of the multiple groups, and the output signals of the multiple time delay devices are collectively logically summed. A phase shift is added to the signal.

[Problem to be solved by the invention]

In the write preshift circuit of the conventional magnetic disk drive described above, it is necessary to prepare the same number of time delay devices as the number of types of delay times to be added, and therefore the same number of signal lines to connect with the time delay devices. is also necessary.

In recent years, magnetic disk drives have rapidly become faster and more dense, and as a result, the number of types of delay times that must be added in write preshift operations has also increased. Further, in recent years, the size of magnetic disk drives has been significantly reduced, and therefore there is a demand for smaller electronic circuits including write preshift circuits and a reduction in the number of signal lines due to integrated circuits.

The problem to be solved by the present invention, that is, the purpose of the present invention is to deal with the increase in the number of types of delay times to be added in the write preshift operation corresponding to the above-mentioned high speed and high density, and to An object of the present invention is to provide a write preshift circuit that can reduce the number of wires and realize electronic circuit miniaturization and integrated circuit integration.

[Means to solve the problem]

The write preshift circuit of the magnetic disk device of the present invention includes:
A shift register that sequentially stores a write pulse train signal, shifts it sequentially, and outputs it; and a shift register that refers to the write pattern of the shift register and distributes it to a plurality of distributed write pattern signals, and at the same timing as the plurality of distributed write pattern signals. a pattern decoder that sends out a pre-distribution write pattern signal, a logic gate that inputs the pre-distribution write pattern signal, a plurality of P-channel oven drain logic gates that input each of the plurality of distribution write pattern signals, and the logic gate. and a time delay device having a plurality of resistors and one capacitor that input the output signals of the plurality of P-channel open train logic gates and add a plurality of different delay times; and the time delay device. In particular, a plurality of P-channel oven-drain logic gates are each configured with a P-channel MOS transistor, and the logic gate and buffer The logic gate is composed of a CMOS type gate.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a write pulse train signal S1 is input to a shift register 1, and a shift register storage pattern signal S2, which is an output signal group of the shift register 1, is input to a butterfly decoder 2. The distributed write pattern signal group S3, which is the output signal of the pattern decoder 2, is input to the P channel open drain logic gate 4, and the pre-distribution write pattern signal S4, which is the second output signal of the pattern decoder 2, is input to the logic gate 3. The output signal group S6 of the P-channel open drain logic gate 4 and the output signal S5 of the logic gate 3 are both input to the time delay device 5,
The output signal S7 of the time delay device 5 is input to a buffer logic gate 6, and the buffer logic gate 6 outputs a write preshift signal 8.

FIG. 2 is a circuit diagram showing details of the time delay device of the embodiment of FIG. 1.

In FIG. 2, a first distributed write pattern signal S9 and a second distributed write pattern signal SIO constituting a distributed write pattern signal group S3, which are the first output signals of the pattern decoder 2, are each a P channel open drain signal. The pre-distribution write pattern signal S is input to logic gates 7 and 8 and is the first output signal of the pattern decoder 2.
4 is input to logic gate 3. P-channel open-drain logic gates 7 and 8 are composed of P-channel MOS transistors Z1 and Z2, respectively, and the drain terminal of P-channel MOS transistor Z1 is connected to capacitor C1 via resistor R1. . Similarly, P-channel MOS transistor Z
The train terminal of 2 is connected to capacitor C through resistor R2.
Connected to 1. The logic gate 3 consists of a CMOS type gate Z3, the output signal S5 of which is connected to a capacitor c1 via a resistor R3. Resistors R1, R2, and R3 and capacitor C1 constitute a time delay device 5. , the output terminal of the time delay device 5,
That is, the connection portions between the resistors R1, R2, and R3 and the capacitor C1 are connected to a buffer logic gate 6 formed of a CMOS type gate, and the buffer logic gate 6 outputs a write shift signal 8.

The source terminals of P-channel MOS transistors Z1 and Z2 are connected to a power supply terminal VCc, and a capacitor C
The other end of 1 is connected to the ground terminal VDD.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

The write pulse train signal S1 is sequentially taken in and stored in the shift register 1. The stored bit pattern is
The signal is input to the pattern decoder 2 as a shift register storage pattern signal S2. The pattern decoder 2 receives two types of distributed write pattern signals S9 and S1. Distribute to O. In addition, distribution line 1 to pattern signals S9 and S1
Pre-distribution write pattern signal S4 at the same timing as 0
Output. Distribution light pattern signals S9 and S10
drive channel open drain logic gates 7 and 8, respectively, to turn on and off current flow into capacitor C1 via resistors R1 and R2. The pre-distribution write pattern signal S4 is sent to a CMOS type gate Z3.
is driven to cause current to flow in and out of the capacitor C1- through the resistor R3. By the above operation, by controlling the on/off of P channel open drain logic gates 7 and 8 when the CMOS gate Z3 is on,
It becomes possible to switch the current flowing into the capacitor C1 when the CMOS gate Z3 shifts to the on state, and the rise time of the potential generated in the capacitor C1 can be switched. The potential developed on capacitor C1 is applied to buffer logic gate 6.
There, the waveform is shaped and output as a write preshift signal 8.

As explained below, this embodiment uses two P-channel M as a P-channel open-drain logic gate group.
By using O8 type transistors, it is possible to set four types of delay times by combining their on/off states.

〔Effect of the invention〕

As described above, the write preshift 1 to circuit of the magnetic disk device of the present invention includes a shift register that sequentially stores write pulse train signals (7) that sequentially shifts and outputs the write pulse train signals;
A pattern decoder that refers to the write pattern of this shift register and distributes it into a plurality of distributed write pattern signals and sends out a pre-distributed write pattern signal with the same timing as the pattern signal; a logic gate into which a signal is input; a plurality of P-channel open drain logic gates into which each of a plurality of distributed write pattern signals is input; and the logic gate t.
- A time delay device having a plurality of resistors and one capacitor that inputs the output signals of the plurality of P-channel open drain logic gates and adds a delay time, and the output signal of this time delay device. By providing a buffer logic gate that inputs, shapes, and outputs the waveform, it is possible to suppress the increase in electronic components and signal lines, and achieve miniaturization and integrated circuits of electronic circuits, which increases the speed of magnetic disk drives and This has the effect that it is possible to increase the delay time for the write 1 reshift drive operation that corresponds to higher density.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing details of the time delay device of the embodiment of FIG. ■...Shift register, 2...Pattern decoder, 3...Logic gate, 4...
・P-channel oven-drain logic gate, 5...
. . . Time delay device, 6 . . . Buffer logic gate, 7. 8 . . . P channel open train logic gate.

Claims (1)

[Scope of Claims] 1. A shift register that sequentially stores a write pulse train signal, shifts it sequentially, and outputs it; A pattern decoder that sends out a pre-distribution write pattern signal with the same timing as the distribution write pattern signal, a logic gate that inputs the pre-distribution write pattern signal, and a plurality of open P channels that input each of the plurality of distribution write pattern signals. A drain logic gate, a plurality of resistors and one capacitor that input the output signals of the logic gate and the plurality of P-channel open drain logic gates and add a plurality of different delay times. A write preshift circuit for a magnetic disk device, comprising: a delay device; and a buffer logic gate that inputs an output signal of the time delay device, shapes the waveform, and outputs the waveform. 2. The magnetic disk device according to claim 1, wherein each of the plurality of P-channel open drain logic gates is composed of a P-channel MOS type transistor, and the logic gate and the buffer logic gate are composed of CMOS type gates. Light preshift circuit.