JPH0449722Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention is applicable to address output circuits, particularly in microcomputer systems composed of a central processing circuit (hereinafter referred to as CPU) and peripheral devices.
Regarding the CPU address output circuit.

[Conventional technology]

Conventionally, this type of address output circuit has been configured to delay and shift the address output control signal for each bit in order to reduce the peak value of the charge/discharge current of the load capacitor.

[Problems to be Solved by the Invention] The conventional address output circuit described above has the disadvantage that it takes a long time to access peripheral devices because it takes time to determine the address value.

In contrast to the conventional address output circuit described above, the present invention divides the output times of the address output signals into two groups, those related to chip select signals and those related to internal address signals, and also sets the delay time of each to the set-up time. It has an original content of reducing the peak value of charging/discharging current and not impairing the access time by setting it in consideration of the standard.

[Means for solving problems]

The circuit of the present invention includes a first delay means that can specify by programming a delay time of an address output buffer that outputs an address signal related to a chip select signal of a peripheral device, and an internal address signal that specifies an internal cell of the peripheral device. A second delay means is provided in which the delay time of the address output buffer to be output can be specified by programming, and the internal address signal or the chip address signal is read out later by the peripheral device out of the chip select signal and the internal address signal by the setup time. It is characterized by being programmed so that it can be read.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Figure 1 shows an embodiment of the present invention, where 1 is a CPU;
2 is a peripheral device accessed by the CPU 1.

Here, it is assumed that the CPU 1 has a standard in which the setup time T _SCS of the chip select signal 9 is smaller than the setup time T _SCEL of the address signal 13 specifying an internal cell, that is, T _SCS <T _SCEL .

Of the address output buffers of the CPU 1, 5 is related to the chip select of the peripheral device 2, and is controlled by the control signal 11;
One of the address output buffers 1 is related to internal cell designation of the peripheral device 2 and is controlled by a control signal 12.

Address signal 7, which is the output of address output buffer 5, is decoded by decoder 3, and the result is supplied to peripheral device 2 as chip select signal 9.

Now, the control signal 11 is set to change by the programmable delay circuit 8 so that each bit is delayed by a delay time T _DELAY from the reference control signal 10, and the control signal 12 is set to change by the programmable delay circuit 6. It is assumed that by setting the time to 0, it is programmed to change simultaneously with the reference control signal 10. In other words, CPU1
When outputting the address, the address signal group 7 and the address signal group 13 are set to be output with a temporal shift of T _DELAY , so the address output circuit's capacitive load is Charging and discharging are performed at different times.

This T _DELAY is specified so as to satisfy T _DEC + T _DELAY < T _SCEL - T _SCS , where T _DEC is the delay time of the decoder 3. As a result, CPU1
The address signal of all bits is the reference control signal 10.
This means that the peripheral device 2 can be accessed at effectively the same timing as when the peripheral device 2 is simultaneously outputted in synchronization with the peripheral device 2, and the access time to the peripheral device 2 is not impaired.

Figure 2 shows that when the delay time due to address output buffers 4 and 5 and wiring etc. is ignored,
a control signal 11 from the point in time when the reference control signal 10 is generated;
It illustrates the time relationship between address signals 7 and 13 and chip select signal 9, and implies that address signal 9 should be read by the time T when peripheral device 2 reads address time 13 (setup time T _SCEL ). This is a time chart that clearly shows the above formula.

The reason why the delay circuits 6 and 8 are provided for each of the address output buffers 4 and 5 in FIG. 1 is that the present invention can be applied to any system in which the number of bits constituting the address signals 7 and 13 is different. This is because consideration has been given to making it applicable.

[Effect of idea]

As explained above, the present invention divides the CPU's address output signals into groups according to the setup time of the peripheral devices connected to the CPU, and can be programmed to output them in a temporally staggered manner. This has the effect of reducing the peak value of the charging/discharging current of the load capacitance of the address output buffer without interfering with the access time to the device.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a time chart of this embodiment. 1...CPU, 2...Peripheral device, 3...Decoder, 4, 5...Address output buffer, 6, 8...
...Delay circuit.

Claims (1)

[Claims for Utility Model Registration] In an address output circuit for a peripheral device, a first delay means capable of specifying, by programming, a delay time of an address output buffer that outputs an address signal to which a chip select signal of the peripheral device relates; A second address output buffer that outputs an internal address signal for specifying an internal cell can be programmed to specify the delay time of the address output buffer.
delay means, and the programming is performed such that the internal address signal or the chip address signal is read by a setup time that is the later of the chip select signal and the internal address signal to be read by the peripheral device. An address output circuit characterized by: