JPH0562787B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a memory block write/read circuit, and is particularly applicable to a pattern data memory write/read circuit in a semiconductor testing device. It is used.

(Prior Art) A writing/reading circuit for a pattern data memory in a semiconductor testing device generally has a logic circuit configuration as shown in FIG. In FIG. 6, 51 is a bidirectional bus driver, 52 is an AND circuit, 53 is a pattern data memory, and 57 is a delay element. Here, the signals on the bus lines BUS1 . Also, BUS1
. . . The BUSn signal is the address information for the pattern data memory blocks 31, 32, . . . 3n and the bidirectional bus driver circuits 11, 12, . . . 1n.
It also serves as block selection information. The selection information of the bidirectional bus driver circuits 11, 12, . . . 1n is sent to the block selection counter 55, and the address information of the pattern data memory 53 is sent to the pattern address.
The counters 56 are each loaded with the SETCK signal. The output of the block selection counter 55 becomes an input signal to the block selection circuit 54, and the block selection circuit 54 selects one of the bidirectional bus driver selection signals S1, S2, . . . Sn.
The signals S1, S2, . . . Sn select the bidirectional bus driver 51 and simultaneously become inputs to the AND circuit 52. S1 is the input signal of the AND circuit 21, S2
is the input signal of the AND circuit 22, and similarly, S3...
...The signals up to Sn become the input signals of the AND circuits 23...2n. These AND circuits 21...2n take the logical product of the WM signal, the CPU signal, and the S1...Sn signal, respectively, and generate a write permission signal (WE) for the pattern data memory 53 to be written. .

In the circuit shown in Figure 6, if the WM signal is "1" (yes), the mode is to write data to the pattern data memory 53, and if it is "0" (no), data is read from the pattern data memory 53. mode. In the case of the write mode, as shown in FIG. 7, the time a cycle for providing write address information and block selection information and the time b cycle for providing write data are processed in a time-division manner. Similarly, in the case of the read mode, as shown in FIG.
Cycles are processed in time division. In either case, address information and block selection information must be given at the same time in a cycle, that is, in the same cycle, so the bus line BUS1...
BUSn will be divided and processed. For example, if pattern data memories 31,...3n are memories of 4096 words x 16 bits, BUS1...
BUS12 becomes address information, BUS13...
BUS16 becomes block selection information. Then,
In this case, 16 blocks of pattern data memory can be handled.

Here, when writing data continuously to the pattern data memory 53, or when reading data continuously from the pattern data memory 53, as shown in FIG. Give the selection value 0 in a cycle, and then continuously apply b2 and b3 from the next b1 cycle.
..., data is read or written. The block selection counter 55 is incremented by 1 count every b cycles, and the pattern data memory 53 is incremented by 31, 32, . . . 3n.
are selected one after another. Block selection counter 5
5 becomes n-1, the block selection counter outputs a carry signal, counts up the pattern address counter 56, and advances the address of the pattern data memory 53. At this time,
The block selection counter returns from n-1 to 0,
It is also counted up from the beginning to n-1,
Pattern address counter 56 is incremented by one. Subsequent reading or writing is performed in the same manner. (Problem to be solved by the invention) Next, a certain one of the pattern data memory 53
When reading data continuously from one memory block or writing data to a memory block, or when reading data from a discontinuous memory block (memory 53
When reading and writing data to (), address information and block selection information must be provided each time as shown in FIG. Therefore, this example has the following drawbacks.

(1) Writing and reading data to and from a discontinuous pattern data memory block always requires both address information and block selection information, so writing and reading only data is impossible.

(2) Writing and reading data to and from discontinuous pattern data memory blocks requires address information and selection information for each piece of data, which increases the writing and reading time.

The present invention has been made in view of the above-mentioned circumstances, and when writing data to or reading data from a pattern data memory in semiconductor testing equipment, etc., it is possible to set address information and block selection information first. , from then on, any pattern data can be input without address information or block selection information.
The purpose of the present invention is to enable continuous writing to or reading from a memory block, and thereby to improve the above-mentioned conventional problems.

(Means and effects for improving the problem) The present invention provides a pattern data memory that stores information for each block, and a pattern data memory that stores information for each block, and a pattern data memory that stores information on a block-by-block basis. A bidirectional bus driver provided, a block selection circuit that selects a block of the pattern data memory, and a block selection circuit that sequentially stores block selection information from the CPU and selects the output of the block selection circuit in accordance with the information. a block select memory, address setting means for writing or reading the pattern data memory;
A register that stores set values by the CPU, a block select counter whose count value changes every time a write or read cycle changes,
an address comparator that compares the output of this counter with the output of the register, resets the block select counter according to the result, and changes the address value of the address setting means; output and the CPU to the block select memory.
This is a memory block write/read circuit characterized in that it is equipped with a multiplexer for switching block selection information from and to the memory block. That is, the present invention provides a circuit for controlling data writing to or reading from a memory block.
By first setting the address information and block selection information using the select memory and its control circuit, it is possible to write or read only data without the need for the CPU to intervene for each data item. , the order of the blocks can be freely executed consecutively.

(Example) An example of the present invention will be described below with reference to the drawings. Although FIG. 1 is a block diagram of the same embodiment, this is an example in which it corresponds to that in FIG.
The same symbols are used for corresponding parts. In FIG. 1, 51 is a bidirectional bus driver circuit 11, 12, . . .
...1n bidirectional bus driver. This bidirectional bus driver 51 stores pattern data memory 53 and bus line signals.
BUS1...A circuit that connects BUSn, its direction is
When the DIR signal is "1" (enabled), it is in the write direction, and if it is "0" (none), it is in the read direction.

AND circuits 21, 22, . . . 2n of 52 are circuits for obtaining a write permission signal WE necessary for writing data into the pattern data memory 53, and block selection signals S1, S2, .
Output when the logical product of the WM signal and CPU signal is established. The WM signal is a signal that determines whether to write or read data to the pattern data memory 53, and is "1" when writing and "0" when reading.
becomes.

The pattern data memory 53 has memory blocks 31, 32, . . . 3n, and the blocks 31, 32, . . . 3n are memories in which function test patterns necessary for semiconductor testing are stored.

The block select memory 67 is the pattern data memory 3 for reading or writing.
1, 32, ...3n and bus line BUS1,
Bidirectional bus drivers 11, 12,...1n that exchange data with BUS2,...BUSn
This memory stores information for selecting the pattern data memory and outputting the write permission signal WE to the selected pattern data memory. This block select memory 67 sequentially takes in and stores block selection information from the bus lines BUS1...BUSn, but this is only when storing the information for the first time.The subsequent operation of the block select memory 67 is based on the block selection information. Leave it to the select counter 68. The block selection circuit 54 is connected to the block selection memory 6.
It decodes the output data signal 0 from 7 and outputs one signal among the output signals S1, S2, . . . Sn. Bidirectional bus driver 51, pattern data memory 53, and AND circuit 52 are selected using these signals S1, S2, . . . Sn.

The pattern address counter 56 is an address counter that sets write and read addresses of the pattern data memory 53. The first address setting is bus line BUS1...
The data on BUSn is loaded into address counter 56 by the SETCK1 signal. Thereafter, the count is increased by the INCP signal applied to the UP input terminal of the pattern address counter 56.

Block select counter 68 is an address counter that sets the address of block select memory 67. The RST input terminal of the block select counter 68 is connected to the pattern
It is cleared by the TR signal before starting data read/write transfer to the data memory 53. Also, to clear the block select counter 68, when writing block selection data to the block select memory 67, clear the TR before writing.
Cleared by a signal.

Loop end register 69 is a register that specifies the loop end address of block select memory 67. Data set to loop end register 69 is via bus line.
BUS1... Address data on BUSn
Set by SETCK2 signal.

Address comparator 70 compares the loop end address set in loop end register 69 with block select counter 6.
This is a digital comparator that detects whether the contents of 8 and 8 match. The block select counter 68 is counted up from 0, and the block select counter 68 is counted up from 0.
1 until it matches the contents of end register 69;
2...and was delayed by delay line 66.
Counted up by CPU signal.
When the contents of both A and B match, a match signal COIN is sent from the A=B terminal of the address comparator 70.
is output.

The AND circuit 72 is a circuit that performs the logical product of the COIN signal and the CUP signal in order to obtain a clear signal for the block select counter 68. this
The output signal of the AND circuit 72 is the delay line 7
After being delayed by 3, it is applied to the RST terminal of block select counter 68 through OR circuit 74, and block select counter 68 is cleared. Multiplexer 71 is a circuit for selecting address data of block select memory 67. The address data selected by this multiplexer 71 is the bus line BUS1...
...There are data given by BUSn and data given from the output Q of the block select counter 68, which are selected by the BS signal. In other words, when the BS signal is "1" (anonymous), the bus line BUS1...
When the address data of BUSn is “0” (none),
Address data output from block select counter 68 is selected.

Next, the operation shown in FIG. 1 will be explained with reference to the time charts shown in FIGS. 2 to 5. First, when writing data to the pattern data memory 53 in FIG.
When reading data from a, as shown in Figure 2,
BUS1 of cycle... Write/read start address/data given by BUSn signal
Set the pattern address counter 56 with the SETCK1 signal. Next, block select
A loop end address necessary for looping the addresses of the memory 67 from address 0 to address X is set in the loop end register 69. This loop end address data is
It is given on the BUS1...BUSn signals of cycle b shown in FIG. 2, and is set in the loop end register 69 by the SETCK2 signal. next
C1 cycle, C2 cycle...then BUS1...
The block selection information given on the BUSn signal is sequentially written in C1 cycle, C2 cycle, and so on. For example, as shown in FIG. 3, an address "0" at which writing or reading from the pattern data memory 53 is to be started is written to the pattern address counter 56 in cycle a. Next, in cycle b, data "2" for using the block select counter 68 as a ternary counter is written in the loop end register 69. This "2" is fixed once written. Also, C1
In the cycle, write the block selection information of the pattern data memory 53 to be written or read for the first time, for example "5", to the address "0" of the block select memory 67, and
In the cycle, write the block selection information of the pattern data memory 53 to be written or read for the second time to address "1" of the block select memory 67, for example "3", and
In the cycle, block selection information of the pattern data memory 53 to be written or read for the third time, for example, "1" is written to the address "2" of the block select memory 67. In the circuit shown in Figure 1, the WM signal is “1” (
If so, the mode is set to write data to the pattern data memory 53, and if it is "0" (none), the mode is set to read data from the pattern data memory 53.

In the write mode, as shown in Figure 4,
The TR signal becomes "0" (none), the reset of the block select counter 68 is released, and
When the BS signal becomes "0" (absent), the multiplexer 71 selects the output signal Q (initial value "0") of the block select counter 68, which becomes the address input of the block select memory 67. .

In the first C1 cycle, the address of the block select memory 67 is "0", and the output 0 is block "5", that is, the block selection circuit 54 is S5.
(not shown) and select Bidirectional Bus Driver 1.
5 (not shown) is selected, and the AND circuit 25 (not shown) selects the S5 signal, WM signal, and CUP signal.
35 of the pattern data memory 53 (not shown)
The data of the bus lines BUS1...BUSn is written to the address "0" of the bus lines BUS1...BUSn. The CUP signal is a pattern
After writing to the data memory 35 is completed, it passes through a delay element 66 and becomes a count-up signal for the block select counter 68, and its output signal Q is incremented by +1.
This indicates the address “1” of 7.

In the second C2 cycle, the address of the block select memory 67 is "1" and the output 0 is block "3", that is, the block selection circuit 54 selects S3, and the bidirectional bus driver 13 (not shown)
is selected, and the AND circuit 23 (not shown) selects S3.
The logical product of the signal, WM signal, and CUP signal is taken and becomes the write enable signal WE, which is used to write the pattern.
The data of BUS1...BUSn is written to address "0" of the data memory 33 (not shown). The CUP signal is the pattern data memory 3
3 (not shown), the block select counter 6 passes through a delay element 66.
8 count up signal, the output signal Q is incremented by 1, and the block select memory 67
This will indicate the address “2” of .

In the third C3 cycle, the address of the block select memory 67 is "2" and the output 0 is block "1", that is, the block select circuit 54 is
S1 is selected, the bidirectional bus driver 11 is selected, and the AND circuit 21 outputs the S1 signal, the WM signal,
The three CUP signals are logically ANDed to become a write permission signal, and the data of BUS1 . . . BUSn is written to address "0" of the pattern data memory 31. At this time, loop end register 69
Since the output signal Q of the address comparator 70 is set to "2" in advance and the block select counter 68 also becomes "2" in the C3 cycle, the input terminals A and B of the address comparator 70 match, and the match output A =B becomes “1” (ant). AND circuit 7
2 and address comparator 70 match output A=
B and the CUP signal are ANDed, and the output signal passes through the delay element 73 and becomes a count-up signal for the pattern address counter 56, so that the pattern address counter 56 is incremented by one.
Further, it passes through the OR circuit 74 and becomes a reset signal for the block select counter 68, the output signal Q becomes "0", and the address of the block select memory 68 returns to the initial value "0". Thereafter, writing is performed in the same manner.

In read mode, TR
The signal becomes "1" (reset), the reset of the block select counter 68 is released, the BS signal becomes "0" (none), and the multiplexer 71
selects the output signal Q (initial value “0”) of the block select counter 68, and selects the output signal Q (initial value “0”)
This serves as an address input for the select memo 67. Also, since the WM signal is “0” (none), the AND circuit 52
Since the AND cannot be taken, the write permission signal is not output.

In the first C1 cycle, the address of the block select memory 67 is "0", the output is block "5", that is, the block select circuit selects S5 (not shown), and the bidirectional bus driver 15 (not shown) is selected. ) is selected, and the contents of address “0” of pattern data memory 35 (not shown) are selected.
BUS1...After being read out to BUSn, delay element 6
The CPU signal passed through 6 becomes the count up signal of the block select counter 68, and its output signal Q is incremented by 1 to indicate the address "1" of the block select memory 67.

In the second C2 cycle, the address of the block select memory 67 is "1" and the output 0 is block "3", that is, the block selection circuit 54 is set to S3.
(not shown) select bidirectional bus driver 13
(not shown) is selected, and the contents of address “0” of pattern data memory 33 (not shown) are
BUS1...After being read out to BUSn, delay element 6
The CUP signal passed through the block select counter 68 becomes the count up signal of the block select counter 68, and its output signal Q is incremented by 1 to indicate the address "2" of the block select memory 67.

In the third C3 cycle, the address of the block select memory 67 is "2", and the output 0 is block "1", that is, the block selection circuit 54 is S1.
is selected, the bidirectional bus driver 11 is selected,
Address “0” of pattern data memory 31
The contents of are read out to BUS1...BUSn. At this time, the output signal Q of the loop end register 69 is set to "2" in advance, and the block select counter 68 also becomes "2" in the C3 cycle, so the input terminals A and B of the address comparator 70 match. is removed, the matching output A=B is “1”
(ant) becomes. The AND circuit 72 performs the logical product of the match output A=B of the address comparator 70 and the CUP signal, and the output signal passes through the delay element 73 and becomes the count up signal of the pattern address counter 56, and the pattern address・The counter is incremented by 1. Further, it passes through the OR circuit 74 and becomes a reset signal for the block select counter 68, the output signal Q becomes "0", and the address of the block select memory 67 returns to the initial value "0". Thereafter, reading is performed in the same manner. Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in FIG. 1, only the bus line to the pattern data memory 51 (via the bidirectional bus driver 51) is connected to the DMA.
(Direct Memory Access) bus line, and can be similarly applied to data writing or reading.

[Effects of the Invention] As explained above, the present invention provides the following effects.

(1) Data writing or reading in discontinuous pattern data memory blocks shall be
By first setting the address information and block selection information in the block select memory,
Thereafter, only data can be written or read continuously without address information or block selection information.

(2) Data writing or reading in discontinuous pattern data memory blocks is
Since the CPU does not need to provide address information and block information for each data, writing or reading time can be shortened.

(3) In discontinuous pattern data memory blocks, the order of blocks in which data is to be written or read can be freely set.

(4) In addition, the present invention has a structure in which each part of the structure can be used for both data writing and reading, that is, it can be used for both writing and reading, so the structure is simplified and the parts used are The advantage is that the number is halved.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIGS. 2 to 5 are time charts showing the operation of the same configuration, FIG. 6 is a configuration diagram of a conventional circuit, and FIGS. 7 to 1
Figure 0 is a time chart showing the operation of the same configuration. 51...Bidirectional bus driver, 52...AND
Circuit, 53...Pattern data memory (31
~3n is a memory block), 54...Block selection circuit, 56...Pattern address counter, 67...Block selection memory, 68
...Block select counter, 69...Loop end register, 70...Address comparator, 71...Multiplexer.

Claims (1)

[Claims] 1 A pattern data memory section that stores information for each block, a bidirectional bus driver section provided between the CPU (central processing unit) bus line and the pattern data memory block, and a write Or when reading, the pattern data to be written or read.
a block selection circuit section that selects a block in the memory; a block selection memory section that sequentially stores block selection information from the CPU and selects an output of the block selection circuit section in accordance with the stored block selection information; an address counter section in which an initial value of an address for writing or reading a block selected in the pattern data memory section is set by the CPU; and a register in which a count setting value is stored by the CPU. The block selection circuit section receives a count signal for each writing or reading cycle, and repeats counting until the count setting value in the register section is reached, and the count data obtained at each count is determined by the count signal. By specifying the address of the block select memory section, a block select counter section selects the output of the block select circuit section, and the output of this block select counter section and the output of the register section are connected. an address comparator section that resets the block select counter section and sends a counting signal to the address counter section if the outputs of these counter sections match the outputs of the register section; - A multiplexer unit that switches between the output of the counter unit and the block selection information from the CPU to the block select memory unit, and a state in which writing of data is prohibited in the pattern data memory unit during reading. At the same time, the data output direction of the bidirectional bus driver section is switched to the bus line side, and at the time of writing, the pattern data memory section is enabled for writing, and the data input direction of the bus driver section is switched to the pattern data memory section. 1. A memory block writing/reading circuit, characterized in that it is equipped with a switching means for switching to the memory block side.