JPH0454375B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a thin film transistor.

[Technical background of the invention and its problems]

Thin film transistors are made using thin films such as amorphous Si, polycrystalline silicon, CdSe, Te, etc.
Its uses include display elements for liquid crystal displays, three-dimensional integrated circuit elements, and combination circuit elements for multifunctional elements.
It is expected that this will continue to spread in the future. The key technologies for improving the performance of thin film transistors are:
These are high-quality thin film formation technology and self-alignment technology. In particular, self-alignment technology for source and drain regions and gate electrodes is important for achieving high-speed operation by miniaturizing elements and reducing gate capacitance when aiming for large-scale integrated circuits.

The basic structure of a thin film transistor is shown in Figure 1~
The one shown in FIG. 3 is known. In FIG. 1, a semiconductor thin film 12 is first formed on an insulating substrate 11,
A source region 13 and a drain region 14 are formed thereon, and a gate insulating film 1 is formed on the channel region.
A gate electrode 16 is disposed through the electrode 5, and a source electrode 17 and a drain electrode 18 are further disposed. Since this structure is basically the same as a MOS transistor using single-crystal silicon, it is easy to form the source and drain regions 13 and 14 by applying self-alignment technology normally used in silicon gate MOS processes. It is.

In FIG. 2, source and drain electrodes 22 and 23 are first formed on an insulating substrate 21, and then a semiconductor thin film 24 is deposited, and source and drain regions 22 and 23 are deposited on this.
5 and 26, and a gate electrode 28 is formed on the channel region with a gate insulating film 27 interposed therebetween. In this structure, as well as the structure shown in FIG. 1, the gate electrode 28 is used as a mask to
It is easy to apply the self-alignment technique to form the drain regions 25 and 26.

FIG. 3 basically has the same structure as FIG. 2, but the order of film formation is reversed. That is, the gate electrode 32 is first placed on the insulating substrate 31.
, a semiconductor thin film 34 is deposited thereon via a gate insulating film 33, source and drain regions 35 and 36 are formed thereon, and source and drain electrodes 37 and 38 are provided. In the structure shown in FIG. 3, since the gate electrode 32 is under the semiconductor thin film 34, conventional self-line technology cannot be applied as is.

[Purpose of the invention]

In manufacturing the above-mentioned thin film transistor shown in FIG. 3, the present invention forms self-aligned source and drain regions on the gate electrode, thereby making it possible to miniaturize the device, increase operating speed, and improve reliability. The present invention provides a method.

[Summary of the invention]

The present invention uses a transparent substrate as an insulating substrate to form the structure shown in FIG. A positive resist film is applied through the film and exposed from the back side of the substrate to form a resist pattern that is self-aligned to the gate electrode, and a semiconductor layer with a high impurity concentration is self-aligned to the gate electrode using this resist pattern as a mask. It is characterized by forming source and drain regions consisting of.

〔Effect of the invention〕

According to the present invention, the thin film transistor having the structure shown in FIG. 3 can be miniaturized and its gate capacitance can be reduced to increase its speed, and it can contribute to improving the performance of integrated circuits, especially when integrated on a large scale.

Furthermore, in the present invention, since the resist is coated on the semiconductor thin film through the insulating film, it is possible to prevent contamination of the semiconductor thin film by the resist and damage to the semiconductor thin film when removing the resist, resulting in a highly reliable thin film transistor. is obtained.

[Embodiments of the invention]

The manufacturing process of one embodiment of the present invention will be explained with reference to FIGS. 4a to 4f. First, an opaque metal gate electrode 42 is formed on a transparent insulating substrate 41, and then a gate insulating film 43 is deposited on the entire surface of the transparent insulating substrate 41.
In addition to insulating materials such as glass, quartz, fired alumina, and sapphire, a semiconductor substrate made of silicon or the like covered with an insulating film can be used as the material.
The gate electrode 42 is made of Al, M ₀ , Ta, Nb, W, Pt
A metal selected from among these metals is used, taking into account the circuit configuration and subsequent thermal process. In addition, the gate insulating film 43
As the material, silicon oxide, silicon nitride, etc. are used by CVD method, sputtering method, etc.

Next, a p-type semiconductor thin film 44 with a low impurity concentration, for example, is deposited on the entire surface (b).The semiconductor thin film 44 is formed of polycrystalline silicon, microcrystalline silicon, or single crystalline silicon to a thickness of about 1 μm or less. These materials have good transparency to visible light, and a mask aligner of about 0.5 μm is sufficient for use with a mask aligner, but since transparency is related to crystal grains, larger crystal grains are better. Therefore, it is desirable to deposit a polycrystalline silicon or microcrystalline silicon thin film and recrystallize it by laser, electron beam, or heat treatment.

Thereafter, an insulating film 45 is deposited on the entire surface by CVD or the like, and then a positive resist film 46 is applied on the entire surface, and the entire surface is exposed to visible light 47 from the back surface of the substrate 41.c. At this time, since the semiconductor thin film 44 does not come into direct contact with the resist film 46 due to the insulating film 45, contamination by the resist film 46 is extremely small.
Then, the resist film 46 is patterned by removing the light irradiated portion, and the insulating film 45 is etched using the remaining resist film 46 as a mask. In this way, a self-aligned resist pattern is formed on the gate electrode 42, and ion implantation 48 is performed ^.
Forming the source region 49 and drain region 50 of the mold e. Impurity diffusion may be performed by thermal diffusion instead of ion implantation. Then, the resist film 46 and the insulating film 45 are removed, and an insulating film 51 is again formed on the entire surface by the CVD method, contact holes are made in this, and the source electrode 52 and the drain electrode 53 are formed.
An n-channel thin film transistor is completed by arranging f.

The specific data is shown below. High purity alumina is used as the substrate 41 and as the gate electrode 42.
A 0.1 μm thick vapor-deposited W film was used, and a 0.1 μm silicon oxide film formed by CVD was used as the gate insulating film 43. Furthermore, as the semiconductor thin film 44, a polycrystalline silicon film with a thickness of about 0.5 μm was deposited at 900°C by low-pressure CVD method, and boron was added to this film with a thickness of 1×10 ¹² cm by ion implantation.
^-2 implantation and recrystallization treatment by laser annealing. On top of this, an insulating film 45 is formed by CVD.
A 0.1 μm silicon oxide film was formed and a positive resist film 46 was applied. After resist pattern formation,
Phosphorus at a dose of 5×10 ¹⁵ cm ^-2 at 80 KeV and
Two-stage implantation was performed using an accelerating voltage of 230 KeV, and the impurities were activated by laser annealing to form a source region 49 and a drain region 50. Laser annealing conditions are power 100mW, spot size 78μ.
m, feed width 40 μm, and feed speed 12.5 cm/sec.

The resulting n-channel thin film transistor has a switching speed of 10 to 15 times faster than a similar structure without self-alignment technology.
% improvement was confirmed.

Another embodiment of the present invention will be described using FIGS. 5a to 5e. The steps up to the formation of the resist pattern are the same as those explained in FIGS ^.
Depositing a type low resistance semiconductor film 54 a. Then, by peeling off the resist film 46, the semiconductor film 54 thereon is lifted off, the insulating film 45 is removed, and unnecessary parts of the remaining semiconductor film 54 are removed by etching to form the source region 54 ₁ and the drain region. 5
4 b forming ₂ . After this, as in the previous example,
The entire surface is covered with an insulating film 51, contact holes are made in this, and a source electrode 52 and a drain electrode 53 are arranged to complete the process c.

In this method, the source and drain regions 54 ₁ ,
The semiconductor film 54 forming 54 ₂ can be used not only as a source and drain region but also as an electrode wiring thereof. Moreover, a suitable metal film can be used instead of the semiconductor film 54.

A specific example according to this embodiment will be explained. Substrate 41
Using Telex glass (product name) as
A gate electrode 42 is made of vapor-deposited Al with a thickness of 0.15 μm, a silicon oxide film with a thickness of 0.1 μm is formed by CVD as a gate insulating film 43, and microcrystalline silicon is deposited with a thickness of 0.2 μm or more by a glow discharge method as a semiconductor thin film 44.
It was formed to a thickness of 0.4 μm. instead of glow discharge method
H ₂ plasma transport method may also be used. Then CVD
After forming a silicon oxide film with a thickness of 0.3 μm, a positive resist film 46 was applied and a resist pattern was formed by exposing the entire surface from the back side. Then, a polycrystalline silicon film containing a high concentration of phosphorus is deposited to a thickness of 0.2 μm and lift-off is applied to the source and drain regions 54 ₁ , 5 .
4 ₂ was formed.

In this example as well, as in the previous example, a high-performance thin film transistor in which the source and drain regions were self-aligned with the gate electrode was obtained.

Further, in the above embodiments, polycrystalline silicon, microcrystalline silicon, or single crystalline silicon is used as the semiconductor thin film, but amorphous silicon may also be used. In this case, since amorphous silicon has large absorption in the visible region, it is desirable to perform crystallization treatment. It is also possible to use it in its amorphous state by adjusting the film thickness, the wavelength sensitivity characteristics of the resist used, the exposure light source, etc.

[Brief explanation of drawings]

FIGS. 1 to 3 are diagrams showing structural examples of thin film field effect transistors, FIGS. 4 a to f are diagrams showing manufacturing steps of one embodiment of the present invention, and FIGS. 5 a to c are diagrams showing other embodiments. It is a figure showing the manufacturing process of. 41...Transparent insulating substrate, 42...Gate electrode, 43...Gate insulating film, 44...Semiconductor thin film, 45...Insulating film, 46...Positive resist film, 47...Visible light, 48... ion implantation, 49
...Source region, 50...Drain region, 51...
... Insulating film, 52, 53 ... Electrode, 54 ... Low resistance semiconductor film, 54 ₁ ... Source region, 54 ₂ ... Drain region.

Claims (1)

[Claims] 1. A step of forming an opaque gate electrode on a transparent insulating substrate, a step of depositing a semiconductor thin film via a gate insulating film so as to cover this gate electrode, and a step of depositing an insulating film on this semiconductor thin film. forming a resist pattern that is self-aligned to the gate electrode by applying a positive resist film through the film and exposing it from the back side of the substrate; and using this resist pattern as a mask to form a resist pattern that is self-aligned to the gate electrode. 1. A method of manufacturing a thin film transistor, comprising the step of forming source and drain regions made of a semiconductor layer with an impurity concentration. 2. The method of manufacturing a thin film transistor according to claim 1, wherein in the step of forming the source and drain regions, impurities are added to the semiconductor thin film using the resist pattern as a mask. 3. The step of forming the source and drain regions involves depositing a low-resistance semiconductor thin film on the semiconductor thin film on which the resist pattern is formed, and leaving this as the source and drain regions by lifting off the resist pattern. 2. A method for manufacturing a thin film transistor according to item 1. 4. The method for manufacturing a thin film transistor according to claim 1, wherein the semiconductor thin film is amorphous silicon.