JPH0454576A - Analog multiplier - Google Patents

Abstract

PURPOSE:To set the output amplitude at a fixed level in an optional phase by providing a capacitor between the collector of a 1st transistor TR and an earth potential or between the collector of a 2nd TR and the earth potential. CONSTITUTION:A capacitor C1 is provided between the collector of a 1st TR Q1 and an earth potential or between the collector of a 2nd TR Q2. Thus some of collector current signals of the Q1 are absorbed by the C1 provided between the collector of the Q1 and the earth potential while these signals are transmitted to the TR Q3 and Q4. Thus no amplitude difference is produced between the signals of the Q3 and a TR Q5 and between the signals of the Q4 and a TR Q6 respectively as long as the proper value of the C1 is selected. In such a constitution, it is possible to obtain an infinite phase unit that has a constant output amplitude in an optional phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog multiplier, and more particularly to an analog multiplier suitable for use in a high frequency band used in wireless communication devices and the like.

[Conventional technology]

Analog multipliers based on double-balanced differential amplifier circuits are suitable for monolithic ICs, and have a wide range of applications such as modulators, demodulators, and automatic gain control amplifiers (AGCAMPs). An infinite phase shifter can be constructed by combining the outputs of two analog multipliers whose phases are 90'' out of phase with each other at one input terminal of each.

A conventional example of such an analog multiplier circuit is shown in FIG.

In the conventional example shown in FIG. 2, transistors Ql, Q3, Q4 and transistors Q2, . Q5. The outputs of the two sets of differential amplifier circuits with Q6 are commonly connected with opposite polarities, and connected to the power supply terminal VCC via load resistors R3 and R4, and the transistors Q1. Q2
The emitters are connected to a constant current source 11 via resistors R1 and R2, respectively.

In the conventional example shown in FIG. 2, since the input signal is a high frequency, it is normally input as an easily handled unbalanced signal and is applied to the INI terminal. Therefore, the other signal input terminal IN2
is grounded at high frequency by a capacitor (not shown).

The signal applied to the input signal terminal INI is transmitted to the collector of the transistor Q1 as a current signal, and at the same time,
Transistor Q2 from the emitter of transistor Q1 through resistors R1, R2 and the emitter of transistor Q2.
appears at the collector of the transistor Q1 as a signal with the same magnitude and opposite polarity as the current signal of the transistor Q1. The collector current signal of transistor Ql is connected to transistor Q3. transmitted from the emitter of Q4 to the respective collectors of transistor Q2.
The collector current signals of are transmitted from the emitters of transistors Q5 and Q6 to their respective collectors. Transistor Q3. Q4 and Q5. The outputs of the two differential circuits made up of Q6 are connected with opposite polarity, so the input terminal IN3
．． If there is no potential difference between IN4, the signals of transistor Q3 and transistor Q5 cancel each other out, and the output terminal ○UTI
No output signal appears. Similarly, the signals of transistor Q4 and transistor Q6 cancel each other out to output terminal 0UT.
No output signal appears in 2 either.

When the potential of input terminal IN3 is higher than the potential of input terminal IN4, the signal of transistor Q3 is higher than that of transistor Q.
5, a signal with the same polarity as the signal of transistor Q3, that is, the same polarity as the signal of transistor Q1, is output to output terminal 0UT1, and the larger the potential difference between input terminals IN3 and IN4, the greater the output signal. growing. Similarly, the transistor Q6 is connected to the output terminal 0UT2.
A signal having the same polarity as the signal of the transistor Q2, that is, the same polarity as the signal of the transistor Q2 is output.

When the potential of input terminal IN4 is higher than the potential of input terminal IN3, the signal of transistor Q5 is higher than that of transistor Q.
3, a signal with the same polarity as the signal of transistor Q5, that is, the same polarity as the signal of transistor Q2, is output to output terminal 0LJT1, and the larger the potential difference between input terminals IN4 and IN3, the greater the output signal. growing. Similarly, the transistor Q is connected to the output terminal 0UT2.
A signal having the same polarity as the signal of transistor Q1 is output.

As described above, input terminal IN3. The magnitude and polarity of the signal output to the output terminal change depending on the potential difference and polarity between IN4. Based on this operating principle, the phases are 90 degrees each other.
``The outputs of the two analog multipliers whose shifted signals are input to the respective input terminals INI are combined, and the outputs of the two analog multipliers are inputted to the input terminals IN3... of the respective analog multipliers. By controlling the potential difference between IN4, an infinite phase shifter can be constructed in which the output signal has an arbitrary phase and a constant amplitude regardless of the phase of the input signal.

[Problem to be solved by the invention]

In order to improve the S/N ratio of the output signal, a relatively high level signal is input to the analog multiplier used in such an infinite phase shifter, so it is necessary to prevent the output from saturating due to its own gain. It is desired that the gain be low. In order to obtain a low gain, in the conventional example shown in Figure 2, the values of resistors R1 and R2 placed on the emitter side of the differential amplifier circuit composed of transistors Q1 and Q2 to which signals are input must be increased. is valid. However, the resistance R1,
By increasing the value of R2, an amplitude difference is created between the collector current signal of transistor Ql and the collector current signal of transistor Q2. That is, since a transistor is generally used in the constant current source 11, a stray capacitance attached to the collector exists between the resistors R1 and R2.

Therefore, while the signal applied to the input terminal INI is transmitted from the emitter of the transistor Q1 to the emitter of the transistor Q2 through the resistors R1 and R2, part of the signal is lost due to this stray capacitance. Therefore, the amplitude of the current signal transmitted from the emitter to the collector of transistor Q2 is smaller than that of the current signal transmitted to the collector of transistor Q1, and the phase difference also deviates from 180°.

Since the value of stray capacitance is very small, this effect has no effect unless the input signal frequency is high, but if you increase the values of resistors R1 and R2 to obtain a low gain, it will affect the frequency actually used. It will affect you. If there is an amplitude difference between the collector current signal of transistor Q1 and the collector current signal of transistor Q2, input terminal IN3. Even when there is no potential difference between IN4, the signal of the transistor Q3 and the signal of the transistor Q5 do not completely cancel each other out, so that an output signal is displayed at the output terminal 0UT1. The same applies to the output terminal 0UT2. In addition, input terminal IN
3. Even if a certain potential difference is applied across IN4 to make the amplitudes of the current signal of transistor Q3 and the current signal of transistor Q5 equal, the phase difference is deviated from 180°, so they will not completely cancel each other out and the current signal will be output to output terminal 0UT1. The same applies to the output terminal 0UT2 where the output signal appears.

As explained above, in order to obtain a low gain, the resistors R1 and R
If the value of IN3.2 is increased, the input terminal IN3. The output signal does not become O regardless of the potential difference between IN4.Therefore, in an infinite phase shifter that combines the outputs of two analog multipliers into which signals whose phases are shifted by 90 degrees from each other is input, the output amplitude can be set to any phase. It cannot be made constant. Further, in order to obtain a constant output amplitude at any phase, input terminals IN3, . There is a problem in that the way to apply the control voltage to IN4 is complicated.

[Means to solve the problem]

The analog multiplier of the present invention includes the first . Second. A first input terminal having third and fourth input terminals, the first and second signal input terminals connected to their respective bases, and each emitter connected to the first constant current source via a resistor. and a second transistor, the third and fourth input terminals connected to their respective bases, their respective emitters connected in common, and third and fourth transistors connected to the collector of the first transistor. and fifth and sixth transistors, the fourth and third input terminals are connected to their respective bases, their respective emitters are commonly connected, and are connected to the collector of the second transistor. and means for extracting an output signal from at least one of a connection point between the collectors of the third and fifth transistors or a connection point between the collectors of the fourth and sixth transistors. A capacitor is provided between the collector of the second transistor and the ground potential, or between the collector of the second transistor and the ground potential.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In FIG. 1, transistors 1 to Q6. Resistance R1~
The analog multiplier consisting of R4 and constant current source 1 has the same configuration as the analog multiplier in the conventional example shown in FIG.
A capacitor C1 is provided between the collector of the transistor Q1 and the ground potential.

In the analog multiplier shown in FIG. 1, the collector current signal of transistor Q2 has a smaller amplitude than the collector current signal of transistor Q1 due to the influence of the stray capacitance of resistor R1°R2 and constant current source 11, as in the conventional example. It is. Here, a portion of the collector current signal of the transistor Q1 is absorbed by the capacitor C1 provided between the collector of the transistor Q1 and the ground potential while the signal is transmitted to the transistors QB and Q4. Therefore, by appropriately selecting the value of the capacitor c1, it is possible to eliminate the difference in amplitude between the signal of the transistor Q3 and the signal of the transistor Q5, and the signal of the transistor Q4 and the signal of the transistor Q6. Also, due to the influence of capacitor C1, transistor Q1
to transistor Q3. Since the phase of the signal transmitted to Q4 is slightly delayed compared to when there is no capacitor C1, the phase difference between the signal of transistor Q3 and the signal of transistor Q5, and the signal of transistor Q4 and the signal of transistor Q6 is 180°. Improved.

FIG. 3 shows the potential difference between input terminals IN5 and IN4 versus output terminal 0L in the conventional example shown in FIG. 2 and the embodiment shown in FIG.
FIG. 3 is a diagram showing the characteristics of the output amplitude of JT1. As seen in FIG. 3, input terminals IN3. The output voltage remaining at the output terminal 0UT1 when IN4 is at the same potential is sufficiently smaller in this embodiment than in the conventional example.

〔Effect of the invention〕

As explained above, the present invention can solve the problem of conventional analog multipliers with low gain in which the output amplitude does not become zero even when the input signal becomes zero. An infinite phase shifter with constant output amplitude in phase can be constructed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram of an example of a conventional analog multiplier, and Fig. 3 shows the characteristics of the conventional example shown in Fig. 2 and the embodiment shown in Fig. 1. FIG. Q1-Q6...transistor, R1-R4...resistor, 11...constant current source, C1...capacitor.

Claims (1)

[Claims] first, second, third and fourth input terminals;
and first and second transistors having second signal input terminals connected to their respective bases and respective emitters connected to the first constant current source via a resistor;
third and fourth transistors, the third and fourth input terminals are connected to their respective bases, their respective emitters are commonly connected, and the collector of the first transistor; and fifth and sixth transistors having third input terminals connected to their respective bases, respective emitters connected in common, and connected to the collector of the second transistor;
and means for extracting an output signal from at least one of a connection point between the collectors of the third and fifth transistors or a connection point between the collectors of the fourth and sixth transistors, wherein the first transistor An analog multiplier characterized in that a capacitor is provided either between the collector of the second transistor and the ground potential, or between the collector of the second transistor and the ground potential.