JPH0520004B2 - - Google Patents
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- Publication number
- JPH0520004B2 JPH0520004B2 JP21303185A JP21303185A JPH0520004B2 JP H0520004 B2 JPH0520004 B2 JP H0520004B2 JP 21303185 A JP21303185 A JP 21303185A JP 21303185 A JP21303185 A JP 21303185A JP H0520004 B2 JPH0520004 B2 JP H0520004B2
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- circuit
- differential amplifier
- amplifier circuit
- differential
- input
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Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積回路化に適した移相回路に関
し、特に入力周波数に対して利得をあまり変化さ
せずに位相のみを360°回転させる移相回路に関す
るものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase shift circuit suitable for integrated circuits, and particularly to a phase shift circuit that rotates only the phase by 360 degrees without changing the gain much with respect to the input frequency. It is related to phase circuits.
従来この種の移相回路として用いられているも
のに第3図に示すものがあつた。図において、1
1は入力端子、21は結合コンデンサ、22,2
3はバイアス用抵抗、31はNPN型トランジス
タ、32,33,34は抵抗、35はコイル、3
6はコンデンサ、80はコイル35、コンデンサ
36からなる直列共振回路、25はNPN型のエ
ミツタフオロワトランジスタ、24はエミツタ抵
抗、12は出力端子、13は電源端子である。
The one shown in FIG. 3 has conventionally been used as this type of phase shift circuit. In the figure, 1
1 is an input terminal, 21 is a coupling capacitor, 22, 2
3 is a bias resistor, 31 is an NPN transistor, 32, 33, and 34 are resistors, 35 is a coil, 3
6 is a capacitor, 80 is a series resonant circuit consisting of a coil 35 and a capacitor 36, 25 is an NPN type emitter follower transistor, 24 is an emitter resistor, 12 is an output terminal, and 13 is a power supply terminal.
この回路の利得と位相の周波数特性例を第4図
に示す。 FIG. 4 shows an example of frequency characteristics of gain and phase of this circuit.
この回路は、部品点数が少なく簡単な回路構成
で第4図に示すような特性を得ることが出来る。
そしてその回路動作は次のようになる。即ち、直
列共振回路80は共振周波数から離れるとインピ
ーダンスが高くなるので、トランジスタ31,2
5共にエミツタフオロワとして動作する。従つ
て、入力信号は、ほぼ利得“1”、位相0°で出力
される。共振周波数においては、直列共振回路8
0のインピーダンスが小さくなり、入力信号は、
トランジスタ31によつて抵抗32,33の比の
利得で反転増幅され、直列共振回路80を経てエ
ミツタフオロワトランジスタ25を通り出力され
る。従つて共振周波数近傍での出力信号は位相
が、180°反転したものになる。なお、この周波数
での利得は抵抗32,33,34の値で自由に設
定できる。 This circuit can obtain the characteristics shown in FIG. 4 with a simple circuit configuration and a small number of parts.
The circuit operation is as follows. That is, since the impedance of the series resonant circuit 80 increases as it moves away from the resonant frequency, the transistors 31 and 2
5 both operate as emitsuta followers. Therefore, the input signal is output with a gain of approximately "1" and a phase of 0°. At the resonant frequency, the series resonant circuit 8
The impedance of 0 becomes small, and the input signal becomes
The signal is inverted and amplified by the transistor 31 with a gain equal to the ratio of the resistors 32 and 33, and is output through the emitter follower transistor 25 via the series resonant circuit 80. Therefore, the output signal near the resonance frequency has a phase inverted by 180°. Note that the gain at this frequency can be freely set by changing the values of the resistors 32, 33, and 34.
しかし、この回路を集積回路化する場合、現在
の技術ではLCの共振回路を内蔵できないので、
入出力端子の他に少なくとも2端子は必要とな
る。また、エミツタ接地増幅回路であるから、電
源電圧のリツプル分がそのまま出力されるという
欠点もある。
However, when making this circuit into an integrated circuit, current technology cannot incorporate an LC resonant circuit.
At least two terminals in addition to the input/output terminals are required. Furthermore, since it is a grounded emitter amplifier circuit, there is also the drawback that ripples in the power supply voltage are output as they are.
この発明は、上記のような従来のものの問題点
を解消するためになされたもので、広帯域にわた
つて利得変化が少なく、位相のみ360°回転する回
路を、端子数が少なく集積回路化に適ししかも電
源電圧リツプルに強い回路とすることができる移
相回路を得ることを目的とする。 This invention was made in order to solve the problems of the conventional circuits as described above, and is suitable for integrated circuits with a small number of terminals and a circuit that has little gain change over a wide band and rotates only the phase by 360°. Moreover, it is an object of the present invention to obtain a phase shift circuit that can be made resistant to power supply voltage ripples.
この発明に係る移相回路は、位相すべき信号が
差動入力される第1の差動増幅回路と、該回路の
差動出力が入力される第2の差動増幅回路と、該
回路と負荷抵抗を共有し第1の差動増幅回路の一
方の出力が直接および抵抗を介して差動入力され
る、上記第2の差動増幅回路の約4倍の利得を有
する第3の差動増幅回路と、該回路と上記抵抗と
の接続点と接地間に接続された直列共振回路とを
設けたものである。
The phase shift circuit according to the present invention includes a first differential amplifier circuit to which a signal to be phased is differentially input, a second differential amplifier circuit to which a differential output of the circuit is input, and a first differential amplifier circuit to which a differential output of the circuit is input. a third differential amplifier circuit that shares a load resistance and receives one output of the first differential amplifier circuit directly and via a resistor, and has a gain approximately four times that of the second differential amplifier circuit; It is provided with an amplifier circuit and a series resonant circuit connected between a connection point between the circuit and the resistor and ground.
この発明においては、非共振時第3の差動増幅
回路の差動入力を同一入力とし共振時第3の差動
増幅回路の差動入力の一方を接地して該回路の出
力を振幅が第2の差動増幅回路出力の約2倍、位
相を逆相する直列共振回路の一端が接地されてい
るから、該直列共振回路の外付け端子が1個で済
む。
In this invention, when non-resonance, the differential inputs of the third differential amplifier circuit are the same input, and when resonant, one of the differential inputs of the third differential amplifier circuit is grounded, and the output of the circuit is Since one end of the series resonant circuit, which has a phase opposite to that of the output of the differential amplifier circuit 2, is grounded, only one external terminal is required for the series resonant circuit.
以下本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例による移相回路を示
し、図において、10,11は差動入力端子、1
2は出力端子、13は電源端子である。またトラ
ンジスタ51,52と抵抗61,62,63,6
4と電流源41は第1の差動増幅回路71を構成
する。トランジスタ53,54はそれぞれ電流源
42,43と共に第1、第2のエミツタフオロワ
回路74,75を構成している。トランジスタ5
5,56はエミツタ抵抗65,66、負荷抵抗6
9、電流源44と共に第2の差動増幅回路72を
構成する。トランジスタ57,58は、エミツタ
抵抗67,68、負荷抵抗69、電流源45と共
に第3の差動増幅回路73を構成している。ここ
で抵抗69は、第2の差動増幅回路と第3の差動
増幅回路の共通の負荷抵抗である。 FIG. 1 shows a phase shift circuit according to an embodiment of the present invention, in which 10 and 11 are differential input terminals;
2 is an output terminal, and 13 is a power supply terminal. Also, transistors 51, 52 and resistors 61, 62, 63, 6
4 and the current source 41 constitute a first differential amplifier circuit 71. The transistors 53 and 54 constitute first and second emitter follower circuits 74 and 75 together with current sources 42 and 43, respectively. transistor 5
5 and 56 are emitter resistances 65 and 66, load resistance 6
9. A second differential amplifier circuit 72 is configured together with the current source 44. The transistors 57 and 58 constitute a third differential amplifier circuit 73 together with emitter resistors 67 and 68, a load resistor 69, and a current source 45. Here, the resistor 69 is a common load resistance of the second differential amplifier circuit and the third differential amplifier circuit.
なお第3の差動増幅回路の差動利得は、第2の
差動増幅回路の差動利得のほぼ4倍になるように
抵抗65,66,67,68、電流源44,45
の値を選んでおく。また第1の差動増幅回路の2
つの出力の振幅が等しくなるように抵抗61と6
2は等しい値としておく。 Note that the resistors 65, 66, 67, 68 and the current sources 44, 45 are used so that the differential gain of the third differential amplifier circuit is approximately four times that of the second differential amplifier circuit.
Select the value of . In addition, 2 of the first differential amplifier circuit
resistors 61 and 6 so that the amplitudes of the two outputs are equal.
Let 2 be the same value.
また本実施例ではコイル35、コンデンサ36
からなる直列共振回路80は、抵抗38と差動増
幅回路73のトランジスタのベースの接続点と接
地間に接続されており、出力信号はトランジスタ
59、電流源46からなるエミツタフオロワ回路
を介して出力端子12より出力される。 In addition, in this embodiment, the coil 35 and the capacitor 36
The series resonant circuit 80 is connected between the connection point of the resistor 38 and the base of the transistor of the differential amplifier circuit 73 and the ground, and the output signal is sent to the output terminal via the emitter follower circuit consisting of the transistor 59 and the current source 46. 12.
この回路の動作は次のようになる。入力端子1
0,11間に差動入力の入力信号を印加すると、
トランジスタ51,52のコレクタに互いに逆相
の増幅出力が得られる。入力信号の周波数が、直
列共振回路80の共振周波数から十分離れた周波
数の時は、第3の差動増幅回路73の入力には同
一の信号が加わり、差動入力はゼロとなる。これ
に対し第2の差動増幅回路72の入力には、前記
第1の差動増幅回路71の差動出力がエミツタフ
オロワ回路74,75を通つて差動入力として印
加される。従つて負荷抵抗69には、第2の差動
増幅回路72の出力が得られ、この信号がエミツ
タフオロワされて出力端子12に伝わる。 The operation of this circuit is as follows. Input terminal 1
When a differential input signal is applied between 0 and 11,
Amplified outputs having opposite phases to each other are obtained at the collectors of the transistors 51 and 52. When the frequency of the input signal is sufficiently distant from the resonant frequency of the series resonant circuit 80, the same signal is applied to the input of the third differential amplifier circuit 73, and the differential input becomes zero. On the other hand, the differential output of the first differential amplifier circuit 71 is applied to the input of the second differential amplifier circuit 72 as a differential input through emitter follower circuits 74 and 75. Therefore, the output of the second differential amplifier circuit 72 is obtained at the load resistor 69, and this signal is emitter-followed and transmitted to the output terminal 12.
次に、入力信号の周波数が直列共振回路80の
共振周波数に等しい時を考える。この場合、共振
回路のインピーダンスはほぼゼロになり、トラン
ジスタ58のベースはほぼ直流になる。従つて第
3の差動増幅回路73には、第1の差動増幅回路
71の出力が片側入力で印加される。第2の差動
増幅回路72には、第1の差動増幅回路71の出
力が差動入力で印加されているので、負荷抵抗6
9には、第2の差動増幅回路72と第3の差動増
幅回路73の出力の和が得られる。この時、第2
の差動増幅回路72の出力は、トランジスタ53
のエミツタから見て逆相、第3の差動増幅回路7
3の出力は同相となり、互いに打ち消し合う。こ
こで第3の差動増幅回路73は、第2の差動増幅
回路72に比べて差動入力に対する利得は約4倍
に設定されており、上述のように第2の差動増幅
回路72は差動入力、第3の差動増幅回路73は
片側入力となるので、第2の差動増幅回路72の
出力振幅に比べると第3の差動増幅回路73の出
力振幅は約2倍となる。従つて、合成されて負荷
抵抗69に得られる出力信号は、共振していない
周波数の時の出力信号と比べて、逆相で振幅のほ
ぼ等しい信号が得られる。 Next, consider a case where the frequency of the input signal is equal to the resonant frequency of the series resonant circuit 80. In this case, the impedance of the resonant circuit becomes approximately zero, and the base of transistor 58 becomes approximately direct current. Therefore, the output of the first differential amplifier circuit 71 is applied to the third differential amplifier circuit 73 as one side input. Since the output of the first differential amplifier circuit 71 is applied to the second differential amplifier circuit 72 as a differential input, the load resistance 6
9, the sum of the outputs of the second differential amplifier circuit 72 and the third differential amplifier circuit 73 is obtained. At this time, the second
The output of the differential amplifier circuit 72 is the output of the transistor 53
The third differential amplifier circuit 7 is in reverse phase when viewed from the emitter of
The outputs of 3 are in phase and cancel each other out. Here, the third differential amplifier circuit 73 is set to have a gain of about 4 times the differential input compared to the second differential amplifier circuit 72, and as described above, the third differential amplifier circuit 73 is a differential input, and the third differential amplifier circuit 73 is a one-sided input, so the output amplitude of the third differential amplifier circuit 73 is approximately twice that of the second differential amplifier circuit 72. Become. Therefore, the combined output signal obtained at the load resistor 69 has an opposite phase and approximately the same amplitude as the output signal at a non-resonant frequency.
この特性を、グラフに示すと第2図のようにな
る。 This characteristic is shown in a graph as shown in FIG.
このように、本実施例によれば広領域にわたつ
て利得をあまり変化させず、位相のみ360°変化さ
せる回路が得られるが、本実施例では直列共振回
路の一端が接地されており、従つて該回路を外付
けするための端子が1個で済み、集積回路化に適
した構成のものが得られる。なお、第1図では入
力端子が2個示されており、従来例より入力端子
数が増加するように見えるが、該入力端子は集積
回路内の本移相回路の前段回路の図示を省略した
ために便宜上図示したにすぎないものであり、従
つて本実施例の回路構成としたことによる入力端
子数の増加はないものである。 In this way, according to this example, a circuit is obtained in which the gain does not change much over a wide area and only the phase changes by 360 degrees, but in this example, one end of the series resonant circuit is grounded, and the Therefore, only one terminal is required for externally connecting the circuit, and a structure suitable for integration into an integrated circuit can be obtained. In addition, although two input terminals are shown in FIG. 1, and it appears that the number of input terminals is increased compared to the conventional example, the input terminals are not shown because the illustration of the preceding stage circuit of this phase shift circuit in the integrated circuit is omitted. This is only shown for convenience, and therefore, there is no increase in the number of input terminals due to the circuit configuration of this embodiment.
また本実施例の移相回路は、差動増幅回路のみ
で構成されているので、電源電圧のリツプルは差
動増幅回路の同相入力となり出力には現れない。 Furthermore, since the phase shift circuit of this embodiment is composed of only a differential amplifier circuit, ripples in the power supply voltage become the in-phase input of the differential amplifier circuit and do not appear in the output.
なお、上記実施例では第2の差動増幅回路と第
3の差動増幅回路の差動利得の比を1:4に選
び、第2図に示すような、利得の周波数特性はほ
ぼ平坦になり、周波数によつて位相は変化する
が、振幅はほとんど変化しないような特性を得た
が、1対4より大きくすると、共振周波数におい
て振幅が大きくなり、逆に1対4より小さくする
と、共振周波数において振幅が小さくなる。この
ように、利得比を選ぶことによつて特性を変化さ
せることが出来る。 In the above embodiment, the ratio of the differential gains of the second differential amplifier circuit and the third differential amplifier circuit is selected to be 1:4, and the frequency characteristics of the gain are almost flat as shown in FIG. We obtained a characteristic in which the phase changes depending on the frequency, but the amplitude hardly changes. However, if the amplitude is made larger than 1:4, the amplitude becomes large at the resonant frequency, and conversely, when it is made smaller than 1:4, the amplitude becomes large at the resonance frequency. The amplitude decreases in frequency. In this way, the characteristics can be changed by selecting the gain ratio.
また、本実施例では直列共振回路はコイルとコ
ンデンサのみであるが、この直列共振回路を抵
抗・コイル・コンデンサの直列回路にしてもよ
い。この場合共振周波数における直列回路のイン
ピーダンスが大きくなるので、トランジスタ58
のベースに抵抗38とこのインピーダンスで分圧
された信号振幅が生じる。この信号はトランジス
タ57のベース信号と同相であるから、等価的に
第3の差動増幅回路73の利得を下げることと同
じである。 Further, in this embodiment, the series resonant circuit includes only a coil and a capacitor, but the series resonant circuit may be a series circuit of a resistor, a coil, and a capacitor. In this case, the impedance of the series circuit at the resonant frequency increases, so the transistor 58
A signal amplitude is generated at the base of the resistor 38 and the voltage divided by this impedance. Since this signal is in phase with the base signal of the transistor 57, this is equivalent to lowering the gain of the third differential amplifier circuit 73.
また本実施例では、トランジスタ58のベース
を直接抵抗38、直列共振回路80に接続してい
るが、製造時のばらつき等によりトランジスタ5
8のhFEが低い場合には第5図に示すようにこの
間に第3のトランジスタ151、電流源47から
なる第3のエミツタフオロワ回路76を挿入して
もよい。この場合トランジスタ55のベースとト
ランジスタ56,57のベースにもエミツタフオ
ロワトランジスタ152,153、電流源49,
48からなる第1、第2のレベルシフト回路7
7,78を挿入して、上記トランジスタ58と直
列共振回路80間にエミツタフオロワを挿入した
ことによるバイアス電圧の変化を補正する必要が
ある。なおこのレベルシフト回路77,78は第
6図に示すようにダイオード161,162で構
成してもよい。 Further, in this embodiment, the base of the transistor 58 is directly connected to the resistor 38 and the series resonant circuit 80, but due to manufacturing variations etc.
If the hFE of 8 is low, a third emitter follower circuit 76 consisting of a third transistor 151 and a current source 47 may be inserted between them as shown in FIG. In this case, the emitter follower transistors 152, 153, the current source 49,
48 first and second level shift circuits 7
7 and 78 to correct the change in bias voltage caused by inserting an emitter follower between the transistor 58 and the series resonant circuit 80. Note that the level shift circuits 77 and 78 may be constructed of diodes 161 and 162 as shown in FIG.
以上のように本発明によれば、第3の差動回路
の差動入力を同一あるいは片側入力とする直列共
振回路の一端を接地するような回路構成としたの
で、集積回路にした時に端子数が少なく、集積回
路化に適ししかも電源電圧のリツプルに強い移相
回路を実現することができる。
As described above, according to the present invention, since the circuit configuration is such that one end of the series resonant circuit in which the differential inputs of the third differential circuit are the same or one side input is grounded, the number of terminals is It is possible to realize a phase shift circuit that is suitable for integrated circuit integration and is resistant to ripples in the power supply voltage.
第1図は本発明の一実施例による移相回路を示
す図、第2図は本発明の一実施例の特性例を示す
図、第3図は従来の移相回路を示す図、第4図は
従来の回路の特性を示す図、第5図および第6図
は本発明の他の実施例を示す図である。
図において、51は第1のトランジスタ、52
は第2のトランジスタ、53は第3のトランジス
タ、54は第4のトランジスタ、55は第5のト
ランジスタ、56は第6のトランジスタ、57は
第7のトランジスタ、58は第8のトランジス
タ、61は第1の抵抗器、62は第2の抵抗器、
38は第3の抵抗器、69は第4の抵抗器、35
は第1のコイル、36は第1の容量、42は第1
の電流源、43は第2の電流源、71〜73は第
1〜第3の差動増幅回路、74〜76は第1〜第
3のエミツタフオロワ回路、80は直列共振回
路、77,78は第1、第2のレベルシフト回
路、161,162はダイオードである。なお図
中同一符号は同一又は相当部分を示す。
FIG. 1 is a diagram showing a phase shift circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a characteristic example of an embodiment of the present invention, FIG. 3 is a diagram showing a conventional phase shift circuit, and FIG. 4 is a diagram showing a conventional phase shift circuit. This figure shows the characteristics of a conventional circuit, and FIGS. 5 and 6 show other embodiments of the present invention. In the figure, 51 is the first transistor, 52
is the second transistor, 53 is the third transistor, 54 is the fourth transistor, 55 is the fifth transistor, 56 is the sixth transistor, 57 is the seventh transistor, 58 is the eighth transistor, 61 is the a first resistor; 62 is a second resistor;
38 is the third resistor, 69 is the fourth resistor, 35
is the first coil, 36 is the first capacitor, and 42 is the first
, 43 is a second current source, 71 to 73 are first to third differential amplifier circuits, 74 to 76 are first to third emitter follower circuits, 80 is a series resonant circuit, 77 and 78 are The first and second level shift circuits 161 and 162 are diodes. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
べき信号が2つの差動入力間に入力される第1の
差動増幅回路と、 該差動増幅回路の差動出力が入力される第1、
第2のエミツタフオロワ回路と、 一方の差動トランジスタのみ負荷抵抗を有し上
記両エミツタフオロワ回路の出力が入力される第
2の差動増幅回路と、 該差動増幅回路の約4倍の利得を有し一方の差
動入力が抵抗を介して他方の差動入力が直接上記
第1のエミツタフオロワ回路の出力にそれぞれ接
続され一方の差動トランジスタが上記第2の差動
増幅回路と上記負荷抵抗を共有するように接続さ
れた第3の差動増幅回路と、 上記抵抗と第3の差動増幅回路との接続点と接
地間に接続された直列共振回路とを備え、 上記第2、第3の差動増幅回路の一方の差動ト
ランジスタと上記負荷抵抗との接続点から出力が
取出されることを特徴とする移相回路。 2 上記直列共振回路は、コイルと容量とからな
るものであることを特徴とする特許請求の範囲第
1項記載の移相回路。 3 上記直列共振回路は、抵抗、コイル、容量か
らなるものであることを特徴とする特許請求の範
囲第1項記載の移相回路。 4 上記抵抗と直列共振回路の接続点と上記第3
の差動増幅回路の一方の入力との間には第3のエ
ミツタフオロワ回路が挿入されており、 上記第1、第2のエミツタフオロワ回路の出力
と上記第2の差動増幅回路の差動入力との間には
上記第3のエミツタフオロワ回路の挿入によるバ
イアス電圧変化を補正する第1、第2のレベルシ
フト回路が挿入されていることを特徴とする特許
請求の範囲第1項ないし第3項のいずれかに記載
の移相回路。[Claims] 1. A first differential amplifier circuit in which each differential transistor has a load resistance and a signal to be phase shifted is input between two differential inputs; the first, where the output is input;
a second emitter follower circuit; a second differential amplifier circuit having only one differential transistor having a load resistance and into which the outputs of both emitter follower circuits are input; and a second differential amplifier circuit having a gain approximately four times that of the differential amplifier circuit; One differential input is connected directly to the output of the first emitter follower circuit through a resistor, and one differential transistor shares the load resistance with the second differential amplifier circuit. and a series resonant circuit connected between a connection point between the resistor and the third differential amplifier circuit and ground, A phase shift circuit characterized in that an output is taken out from a connection point between one differential transistor of the differential amplifier circuit and the load resistor. 2. The phase shift circuit according to claim 1, wherein the series resonant circuit comprises a coil and a capacitor. 3. The phase shift circuit according to claim 1, wherein the series resonant circuit comprises a resistor, a coil, and a capacitor. 4 The connection point between the above resistor and the series resonant circuit and the above third
A third emitter follower circuit is inserted between the outputs of the first and second emitter follower circuits and the differential input of the second differential amplifier circuit. Claims 1 to 3 are characterized in that first and second level shift circuits are inserted between them for correcting bias voltage changes caused by insertion of the third emitter follower circuit. The phase shift circuit described in either.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21303185A JPS6272217A (en) | 1985-09-26 | 1985-09-26 | phase shift circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21303185A JPS6272217A (en) | 1985-09-26 | 1985-09-26 | phase shift circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6272217A JPS6272217A (en) | 1987-04-02 |
| JPH0520004B2 true JPH0520004B2 (en) | 1993-03-18 |
Family
ID=16632361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21303185A Granted JPS6272217A (en) | 1985-09-26 | 1985-09-26 | phase shift circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6272217A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2744354B2 (en) * | 1991-02-07 | 1998-04-28 | 沖電気工業株式会社 | Constant amplitude phase shift circuit |
| JP2744355B2 (en) * | 1991-02-07 | 1998-04-28 | 沖電気工業株式会社 | Constant amplitude phase shift circuit |
| US6452434B1 (en) | 2000-01-27 | 2002-09-17 | Fujitsu Limited | Phase shifter circuit |
-
1985
- 1985-09-26 JP JP21303185A patent/JPS6272217A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6272217A (en) | 1987-04-02 |
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