JPH0454660A - Data transfer controller - Google Patents

Abstract

PURPOSE:To execute a normal data transfer between an MPU and a peripheral equipment by providing a data transfer error preventing configured by a true response signal generating means and an inversion output means. CONSTITUTION:When a response signal from a RAM 21 of the previous cycle is delayed and inputted to a data transfer error preventing circuit 30, when an external cycle start signal remains a high level and a first external cycle start signal of a processing of the next cycle is not outputted, a response signal enable signal from an FF 31 remains a low level. Accordingly, the response signal from the RAM 21 is transferred as a true response signal to an MPU 10. Subsequently, when the external cycle start signal of the next cycle is outputted, the response signal enable signal from the FF 31 is transferred from a low level to a high level. As a result, even if the delayed response signal from the RAM 21 is inputted to the data transfer error preventing circuit 30, the true response signal is transferred to a high level being an initial level by synchronizing with a transition of the response signal enable signal. Accordingly, the delayed response signal is not transferred to the MPU 10.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a data transfer control device between a microprocessor and peripheral devices constituting a microcomputer.

[Prior art]

Conventionally, a microprocessor (hereinafter referred to as rMPU) constituting a microcomputer has been used as a peripheral device such as R
When data is transferred to/from the AM, the MPU first accesses the RAM (the select signal and the read/write signal reach the RAM), as shown in FIG. Next, after the timer circuit, which is set in advance for the time required for reading/writing between the MPU and the RAM, has timed up, the RA
M outputs a response signal to the MPU to notify the completion of data transfer. Then, when the MPU recognizes the response equal sign, it ends the processing of the previous cycle and moves on to the processing of the next cycle.

[Question B that the invention attempts to solve]

At the end of the cycle, the response signal is turned off based on a select signal turned off in the peripheral device and transmitted to the MPU. In order to perform accurate data transfer, it is necessary to prevent the turning off of this response signal from being recognized at the recognition timing of the response signal of the MPU in the next cycle. However, MPU! : If the peripheral device is connected far away, there will be a delay during data transfer, and even if the response signal is turned off in the peripheral device, it will not be turned off immediately in the MPU. Therefore, the distance between the MPU and peripheral devices is limited. Further, there is a problem in that normal data transfer cannot be performed if a delayed response signal from a peripheral device from a previous cycle is received at the recognition timing of the MPU's response signal for the next cycle. The present invention has been made to solve the above problems, and its purpose is to solve the problem even if the MPU and peripheral devices are connected apart and there is a delay during data transfer. An object of the present invention is to provide a data transfer control device that can normally transfer data between an MPU and peripheral devices.

[Means to solve the problem]

The configuration of the invention for solving the above problem is a data transfer control device disposed near the MPU between an MPU and a peripheral device, the data transfer control device being configured to transfer data from the peripheral device to the MPU.
inputs a response signal that indicates the completion of data transfer to move on to the next cycle of processing, and generates a true response signal whose level changes in synchronization with the response signal's transition to the level indicating the response completion state. A true response signal generating means, and a response of the true response signal generated by the true response signal generating means in synchronization with the generation timing of a cycle start signal for synchronizing the processing cycle of the MPU. The present invention is characterized in that it includes a data transfer error prevention circuit constituted by an inverting output means for outputting to the MPU the transition to an initial level opposite to the level indicating the completion state.

[Effect]

The true response signal generating means of the data transfer error prevention circuit inputs a response signal output from the peripheral device and informing the MPU of the completion of data transfer for moving on to the next cycle of processing;
A true response signal whose level changes in synchronization with the transition of the response signal to a level indicating a response completion state is generated. Then, the signal inversion means of the data transfer error prevention circuit converts the true response signal generated by the true response signal generation means into the MP
In synchronization with the generation timing of a cycle start signal for synchronizing the processing cycle of U, the response signal is made to transition to an initial level opposite to the level indicating the response completion state and is output to the MPU. In other words, even if the MPU and the peripheral device are connected far apart and the response signal from the peripheral device is delayed, the data transfer error prevention circuit will recognize the response signal of the previous cycle at the recognition timing of the next cycle by the MPU. It will not be done.

【Example】

The present invention will be described below based on specific examples. FIG. 1 is a block diagram showing a data transfer control device equipped with a data transfer error prevention circuit according to the present invention. In the embodiment, a signal with a line drawn above the name, etc. indicates that it is a low active signal that becomes effective when its level is low. The MPUl0 constituting the micro combinator and the peripheral device 20, for example, the RAM 21, are connected separately,
It shows data transfer between MPU10 and RAM21. The MPU10 and the RAM 21 are connected by an address bus and a data bus, and also by a select signal line, a response signal line, a true response signal line, a read/write signal line, and the like. A data transfer error prevention circuit 30 is provided near MPU10 between the response signal line and the true response signal line. The data transfer error prevention circuit 30 is a set/reset flip-flop circuit (hereinafter referred to as a "flip-flop circuit").
) 31, a negative logic OR circuit (hereinafter referred to as "FOR circuit") 32, and inverters 33 and 34. The response signal line from the RAM 21 is connected to the D terminal of the flip-flop circuit 31 and one input terminal of the OR circuit 32. Further, the response signal line from the RAM 21 is connected to the S of the flip-flop circuit 31 via the inverter 33.
connected to the terminal. Moreover, the flip-flop circuit 31
The Q terminal of is connected to the other input terminal of the OR circuit 32. Furthermore, the MPU is connected to the CK terminal of the flip-flop circuit 31.
The external cycle start signal line that transmits the cycle start signal for synchronizing the processing cycle of l0 is connected to the MPU.
It is connected from l0 via an inverter 34. or,
The output terminal of the OR circuit 32 is connected to MP via the true response signal line.
It is connected to U,10. Note that the reference voltage V is applied to the R terminal of the flip-flop circuit 31.
. C is applied, and the Q terminal is an empty terminal. The flip-flop circuit 31 outputs the signal input to the D terminal from the G terminal at the falling timing of the signal input to the CK terminal. Furthermore, since the MPU10 and the RAM 21 of the peripheral device 20 are separated, there is a delay between them. Next, MPU10 in the data transfer control device of the present invention
This will be explained with reference to FIG. 2, which shows the operation timing of the RAM 21 of the peripheral device 20. The external cycle start signal is output once at the beginning of each processing cycle to synchronize the processing cycles of MPU10. When a response signal informing the data transfer completion from the RAM 21 to the MPU10 is input to the data transfer error prevention circuit 30, an output signal from the data transfer error prevention circuit 30 is output in synchronization with the transition of the response signal to the level indicating the response completion state. The level of changes. This output signal immediately transitions to the initial level if the response signal from the RAM 21 is input at the falling timing when the external cycle start signal becomes valid. In this embodiment, when the level of the response signal enable signal on the signal line connecting the flip-flop circuit 31 and the OR circuit 32 of the data transfer error prevention circuit 30 is low, the response signal from the RAM 21 is converted into a true response signal. as MP
- communicate to UIO. Then, when the response signal enable signal transitions from a low level to a high level, the response signal from the RAM 21 is
Not transmitted to PU10. The level transition of the response signal enable signal is achieved by the data transfer error prevention circuit 30. Assume that the response signal from the RAM 21 in the previous cycle is input to the data transfer error prevention circuit 30 with a delay. At this time, if the external cycle start signal remains at a high level and the first external cycle start signal for the next cycle is not output, the response signal enable signal from the flip-flop circuit 31 remains at a low level. Therefore, the response signal from RAM 21 is treated as a true response signal by MP.
It is transmitted to Ul0. Then, when the external cycle start signal of the next cycle is output, the response signal enable signal from the flip-flop circuit 31 changes from low level to high level. Then, even if the delayed response signal from the RAM 21 is input to the data transfer error prevention circuit 30, the true response signal is transitioned to a high level, which is the initial level, in synchronization with the transition of the response signal enable signal. Therefore, the delayed response signal is not transmitted to MPU10. In this way, the output signal from the data transfer error prevention circuit 30 is transmitted as a true response signal to M via the true response signal line.
It is transmitted to PU10. As described above, by using the data transfer control device of the present invention, normal data transfer between the MPU 10 and the peripheral device 20 is possible without being limited by the distance between the MPU 10 and the peripheral device 20. Become.

【Effect of the invention】

The present invention inputs a response signal that is output from a peripheral device and informs the MPU of the completion of data transfer for moving on to the next cycle of processing, and raises the level in synchronization with the transition of the response signal to a level indicating a response completion state. A true response signal generation means for generating a true response signal to which the true response signal is transitioned, and generation of a cycle start signal for synchronizing the processing cycle of the MPU with the true response signal generated by the true response signal generation means. It is equipped with a data transfer error prevention circuit consisting of an inverting output means that synchronizes with the timing and transitions the response signal to an initial level opposite to the level indicating the response completion state and outputs it to the MPU. This prevents the inconvenience that an incorrect response signal caused by a delay in data transfer during the process is recognized at the recognition timing of the next cycle of the MPU. Therefore, there is an effect that normal data transfer can be performed between the MPU and peripheral devices whose connection distances are freely set.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data transfer error prevention circuit of a data transfer control device according to a specific embodiment of the present invention. FIG. 2 is an operation timing diagram of the MPU and peripheral devices in the pig transfer control device of the present invention. FIG. 3 is a block diagram showing a conventional data transfer control device. 10-MPU 20 Peripheral device 21-RAM30
°Data transfer error prevention circuit 31--Flip-flop circuit (Flip-flop circuit with set/reset) 32-OR circuit (Negative logic OR circuit) 33.34-°-Inverter

Claims (1)

[Scope of Claims] A data transfer control device disposed near the microprocessor between a microprocessor and a peripheral device, wherein the data transfer control device is configured to control data transfer between a microprocessor and a peripheral device, the data transfer control device being configured to transfer data from the peripheral device to the microprocessor in order to move on to the next cycle of processing. a true response signal generating means for generating a true response signal whose level is changed in synchronization with the transition of the response signal to a level indicating a response completion state; The true response signal generated by this true response signal generation means is synchronized with the generation timing of a cycle start signal for synchronizing the processing cycle of the microprocessor, and is opposite to the level indicating the response completion state of the response signal. 1. A data transfer control device comprising: a data transfer error prevention circuit configured with an inverting output means for transitioning the signal to an initial level and outputting the signal to the microprocessor.