JPH0454713A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To attain the signal processing for a high frequency through the use of the processing circuit for a low frequency band by providing a sample and hold circuit in response to a prescribed sampling phase to the signal processing circuit, and outputting a value sampled sequentially at a prescribed period as a time series analog signal. CONSTITUTION:When an analog signal is inputted to an input buffer amplifier 30, each of sample and hold circuits 1-8 samples an analog input signal at a prescribed phase for a prescribed sampling period, and outputs the result to amplifiers 21-28. Thus, the analog input signal is converted into plural analog signals having a frequency of the sampling period separated for a prescribed phase as a maximum frequency. Since the high frequency analog input signal is converted into plural analog signals with a low frequency almost equivalent to the input signal separated according to a predetermined phase difference, a general-purpose inexpensive circuit for a low frequency band is applied to a post-stage signal processing circuit, high circuit integration of the signal processing system is facilitated and the cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Use) The present invention relates to a signal processing circuit that separates and converts a high-speed analog signal into a plurality of low-speed analog signals.

(Prior Art) Conventionally, analog signals have been subjected to signal processing such as amplification and filtering by one system of signal processing circuits that can process a frequency band including the highest frequency included in the analog signal. Ta.

[Problem to be solved by the invention]

The above-mentioned conventional signal processing circuits require a high-grade circuit configuration when the frequency of the analog input signal is high, resulting in high costs.In addition, signal processing circuits with a sufficient frequency band are not easily available, and even more advanced integration is required. The disadvantage is that it is not possible to realize highly integrated circuits.

An object of the present invention is to provide a signal processing circuit capable of processing higher frequency signals using an analog signal processing circuit with a low wheel frequency band.

[Means to solve the problem]

The signal processing circuit of the present invention includes: a receiving section for receiving an analog input signal; and a receiving section for receiving the received analog signal at each predetermined sampling phase, connected in parallel to the receiving section, and each receiving section for receiving the input analog signal. It has a plurality of sample and hold circuits that sequentially sample and hold data at a predetermined period and output the sampled values as time-series analog signals according to the period.

[For production]

When an analog signal is input, a sample hold circuit connected in parallel to the human input section samples and holds the analog signal value for each predetermined phase, and within each output cycle, the time series of each phase of the human input signal is generated. Since it is output as an analog signal, it can be output as a plurality of analog signals for each predetermined phase converted to a frequency of a predetermined sampling period.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of a signal processing circuit according to the present invention, and FIG. 2 is a diagram showing each sample and hold circuit 1 of the signal processing circuit shown in FIG. ~． Figure 8 shows a sampling sequence of 8;
Figure 3 (a), (b).

~, (i) shows the human input signal waveform of the signal processing circuit shown in FIG. 1 and each sample and hold circuit 1. FIG. 8 is a diagram showing sampling states and output signal waveforms of .

This signal processing circuit includes an input buffer amplifier 30 to which an analog signal is input, and eight sample and hold circuits 1. ~．
8, and an amplifier 21.8 directly connected to each output terminal of each sample hold circuit 1.about.8. ~． Consists of 28. The manual buffer amplifier 30 is connected to the next stage sample and hold circuit 1. At the same time, the sample and hold circuits 1. to 8 are prevented from affecting the input signal. ~． 8 serves to provide a sufficiently low impedance for operation. Each sample and hold circuit1. 8 are connected in parallel to the input buffer amplifier 3o, and sample the values at the phases of the analog input signals cyclically determined in advance in the order shown in FIG. ．． ~． Output to 28.

Next, the operation of this embodiment will be explained.

When the analog signal shown in FIG. 3(a) is input to the manual buffer amplifier 30, the sample-hold circuit I performs a predetermined period of time t for each predetermined sampling period as shown in FIG. 3(b).
ll+ j2++ t31+ t41゜j5++
At t61, the value of a predetermined phase of the analog human input signal is sampled and output to the amplifier 21, and the sample hold circuit 2 samples the value of the predetermined phase of the analog human input signal from time t21 to time t32.t32 for each sampling period as shown in FIG. 3(e). t4□+t
At S2+t62, the sample-and-hold circuit 1 samples the next phase value of the analog input signal and outputs it to the amplifier 22. Similarly, sample hold circuit 3. ~． 8 is the time t13+~I t1831... as shown in FIG. 3(d), ~, (i), respectively.
~jlls+~t68. ..., the phase value of the analog input signal assigned to each is sampled and amplified @23. ~, 28. As a result, the analog human input signal is converted into a plurality of analog signals separated for each predetermined phase and whose highest frequency is the frequency of the sampling period.

FIG. 4 is a block diagram of a second embodiment of the signal processing circuit of the present invention, and FIG. 5 shows each sample and hold circuit 1 of the signal processing circuit shown in FIG. ~． 8.41. ~． Figures 6(a), 6(b), . 8 sampling sequences and amplifiers 21, . 28 is a diagram showing the output signal waveform of No. 28.

This signal processing circuit is the sample hold circuit 1 of the first embodiment. ~． 7 and amplifier 21. ~． Sample and hold circuits 41, . 47 is inserted, and the sample bold circuit 41. ~． Reference numerals 47 and 47 respectively designate sample and hold circuits 1. and 47 in the same manner as in the first embodiment. ~． 7
When the sample and hold circuit 8 outputs in the same sampling period, the values outputted by the sample and hold circuit 8 are amplified 1121° to 2 as shown in FIG.
Output to 7.

That is, ′! As shown in Figure J6, this signal processing circuit uses the value of the analog input signal sampled by the sample and hold circuit 1 at time t11 to the sample and hold circuit 41.
is held and output to the amplifier 21 at time tag, and the sample and hold circuit 2. ~． 7 respectively at time t12. ～+
The value of the analog input signal sampled at t17 is sent to the sample and hold circuit 42, . 47 holds time tll
B to each amplifier 22. ~． Output to 27. As a result, each term width unit 21. ~． The signals appearing at the outputs of 28 are synchronized and have the frequency of the sampling period, and are analog output signals separated for each predetermined phase.

FIG. 7 is a block diagram of a third embodiment of the signal processing circuit of the present invention, and FIG. 8 is a sample hold circuit 1 of the signal processing circuit shown in FIG. ~． 8.41. ~． 48 and switch 11. ~．
18 is a sequence diagram.

This signal processing circuit includes sample and hold circuits 1, . 8
and 41. ~． Two groups of 48 are connected in parallel to the input buffer amplifier 30, sample and hold circuits 1 and 41.2.
and 42, . . . 8 and 48 are respectively switches 11. ~
．． 18 via amplifier 21. ~． 28 at the same time and alternately. Therefore, in this signal processing circuit, after the input circuit is connected, the switch 11. ~． 18 at the same time as the sample and hold circuit 41. ~． 48 side, the sample hold circuit 41. . . . . . . . . . . . . . to . ~． 28
output to switch 11. in the next output cycle. ~． 18 switches, the sample hold circuit 1. ~． 8 outputs the values of the analog human input signals that have already been sampled and held to amplifier circuits 21 . ~． 28 at the same time, synchronized output is performed as in the second embodiment. However, in the case of the third embodiment, since the signal path is shorter than that in the second embodiment, it has the advantage that a relatively high S/N ratio can be obtained.

〔Effect of the invention〕

As explained above, the present invention converts a high frequency analog human input signal into multiple low frequency approximately equivalent analog signals separated according to a predetermined phase difference. This has the effect of making it possible to apply low-cost, general-purpose, and inexpensive circuits, facilitating high integration of signal processing systems, and reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of a signal processing circuit according to the present invention, and FIG. 2 is a diagram showing each sample and hold circuit 1 of the signal processing circuit shown in FIG. Figure 3 (a), (b), ~ (i
) is the input signal waveform of the signal processing circuit shown in FIG. 1 and each sample hold circuit 1. A diagram showing the output signal waveform of ~,8,
FIG. 4 is a block diagram of a second embodiment of the signal processing circuit of the present invention, and FIG. 5 shows each sample and hold circuit 1 of the signal processing circuit shown in FIG. ~． 8.41. ~． FIG. 6(a) is a diagram showing a 4-f sampling sequence. (b), ~, (i) The input signal waveform of the signal processing circuit shown in Fig. 4, the sampling sequence of each sample and hold circuit 1~, 8, and the amplifier 21~, . 7 is a configuration diagram of the third embodiment of the signal processing circuit of the present invention, and FIG. 8 is a diagram showing the output signal waveform of the signal processing circuit 1.28 shown in FIG. ~
．． 8.41, ~. 48 sampling sequences and switches 11. ~． 18 is a diagram showing the timing of No. 18. FIG. 1, ~. 8.41, 7.48--Sample and hold circuit, 11,~,18--Switch, 21,~,28--Amplifier, 30--Input buffer amplifier.

Claims (1)

[Claims] 1. A receiver for receiving an analog input signal, each of which is connected in parallel to the receiver and is provided for each predetermined sampling phase to receive the received analog signal. A signal processing circuit including a plurality of sample and hold circuits that sequentially sample and hold the values at a predetermined period and output the sampled values as time-series analog signals according to the period. 2. The signal processing circuit according to claim 1, wherein the sample and hold circuit is an analog delay circuit.