JPH0455151U - - Google Patents

Info

Publication number
JPH0455151U
JPH0455151U JP1990097169U JP9716990U JPH0455151U JP H0455151 U JPH0455151 U JP H0455151U JP 1990097169 U JP1990097169 U JP 1990097169U JP 9716990 U JP9716990 U JP 9716990U JP H0455151 U JPH0455151 U JP H0455151U
Authority
JP
Japan
Prior art keywords
external connection
semiconductor device
power semiconductor
end side
boards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990097169U
Other languages
English (en)
Other versions
JPH0810950Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990097169U priority Critical patent/JPH0810950Y2/ja
Publication of JPH0455151U publication Critical patent/JPH0455151U/ja
Application granted granted Critical
Publication of JPH0810950Y2 publication Critical patent/JPH0810950Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Combinations Of Printed Boards (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例の切断左側面図、第
２図はそれの平面図、第３図はそれの正面図、第
４図は従来装置の切断側面図である。 ２，６……基板、３ａ，３ｂ……電子部品、４
……コネクタ（外部接続用部材）、５……端子（
外部接続用部材）、７ａ，７ｂ……電力半導体素
子、９……モールド樹脂、１１……外枠ケース。

Claims (1)

    【実用新案登録請求の範囲】
  1. ２枚の電子部品実装基板がそれらの各実装面を
    向かい合わせて配置され且つそれらの各外部接続
    用部材を同一方向に外部突出させて外枠ケースに
    取り付けられているとともに、前記両基板間がモ
    ールド樹脂を充填して封止された電力半導体装置
    において、前記２枚の基板の間隔を、前記外部接
    続用部材を有する一端部側間に対し反対側の他端
    部側間を狭くしたことを特徴とする電力半導体装
    置。
JP1990097169U 1990-09-14 1990-09-14 電力半導体装置 Expired - Fee Related JPH0810950Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990097169U JPH0810950Y2 (ja) 1990-09-14 1990-09-14 電力半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990097169U JPH0810950Y2 (ja) 1990-09-14 1990-09-14 電力半導体装置

Publications (2)

Publication Number Publication Date
JPH0455151U true JPH0455151U (ja) 1992-05-12
JPH0810950Y2 JPH0810950Y2 (ja) 1996-03-29

Family

ID=31837300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990097169U Expired - Fee Related JPH0810950Y2 (ja) 1990-09-14 1990-09-14 電力半導体装置

Country Status (1)

Country Link
JP (1) JPH0810950Y2 (ja)

Also Published As

Publication number Publication date
JPH0810950Y2 (ja) 1996-03-29

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees