JPH0456518A - A/d conversion unit - Google Patents

Abstract

PURPOSE:To obtain A/D conversion resolution improved by one bit more with respect to a bit number obtained from an A/D converter in use by employing a circuit comprised of the combination of two analog signal input circuits. CONSTITUTION:With jumpers JP1-JP3 selected to the position of a terminal A, the output of an operational amplifier 32 of an analog signal input circuit 22 is connected to the inverting input terminal of an operational amplifier 33 of an analog signal input circuit 23 so that the output of the operational amplifier 32 is summed to a voltage from a reference power supply IC 5 and the output of the operational amplifier 33 is fed to the input terminal i3 of an A/D converter 1. In such a case, a same analog signal is simultaneously inputted to the analog signal input circuits 22, 23 and a prescribed sequence program is executed by a sequencer to improve the A/D conversion resolution of the 8-bit A/D converter 1 into 9-bit resolution. Thus, the A/D conversion resolution is improved by one bit more with respect to a bit number obtained from an A/D converter in use.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applied to an A/D conversion unit which is a peripheral device of a sequencer.

[Prior Art] FIG. 5 shows a block diagram of an A/D conversion unit of a conventional sequencer.

This A/D conversion unit converts 4 analog signals into 8
The A/D converter 1, which is the main part of the A/D conversion operation, converts into bit digital signals, and converts four analog signals in the input voltage range O to 5 to input terminals 10 to i, depending on the selection. Is it an 8-bit digital signal D0-D? (0 to 255 in decimal).

Analog signal input circuits 2° to 2, which are provided corresponding to the four signal input channels CH0 to CH3, are each provided with jumper switches JPo, and when the A terminal is on, the analog signal input terminals are connected to the analog signal input terminals. The input range of
As shown in figure (a), the current limiting resistor R1 is 0 to 5■,
A through op amp 3 which acts as a voltage follower
/D converter 1.

When the B terminal of the jumper switch JP is on, the values of the resistors R, and R2 are set to the same value, so the input range to the analog signal input terminal ■ is 0 to IOV as shown in Figure 6(b). Become.

) The diodes d and d are such that the output from the operational amplifier 3 is 15~
This is an input protection diode added to prevent the A/D converter 1 from being destroyed even if an input signal of OV, 5 to IOV is input.

Further, the reference power supply IC 5 is a power supply circuit for supplying the reference voltage ■□ to the A/D converter 1.

Thus, four analog signal input circuits 2° to 2. When the analog signal from the bus I/F circuit 4 is selected by the 2-bit select signal SEL, , SEL and the readout signal plane and converted by the A/D converter 1, the digital value obtained by the conversion is The sequencer's cp via the sequencer's I10 bus consisting of the bus I/F circuit 4, data bus DB, address bus AB and read signal RDB
u (not shown).

The conventional A/D conversion unit configured in this manner has an 8-bit resolution (1/256) for both input ranges of 0 to 5 V and 0 to IOV.

[Problem to be solved by the invention] However, as mentioned above, the conventional A/D conversion unit has 8
Although the resolution is assumed to be bit resolution, when considering the actual circuit components, the analog signal input circuit has a resolution of 2 to 2 degrees. The resistors R, ,R, the operational amplifier 3, and the A/D converter 2 each contain errors due to component variations, so at least the least significant bit of the 8-bit digital value converted from A/D contains errors, and in actual use, the lower internal bits of the 8-bit digital value taken into the sequencer's CPU are often discarded, and the 7 bits other than the lowest are used for control in the sequencer.

Therefore, especially in the case of a wide range of 0 to 10 V, control is performed in units of 1/128 of IOV using only 7 effectively effective bits, making it impossible to precisely incorporate changes in the input analog amount into the sequencer.

The present invention has been made in view of the above-mentioned problems, and its purpose is to obtain an A/D converter with a 9-bit resolution even when using an 8-bit resolution A/D converter. To provide a D conversion unit.

[! l! [Means for Solving the Problem] In order to achieve the above object, the invention according to claim 1 includes an A/D converter that inputs a plurality of analog signals separately and converts each into a digital value of a fixed number of bits. , the A/D
A first analog signal input circuit that inputs and outputs an analog signal up to twice the maximum value of the analog signal that can be input to the converter, and an analog signal that is input to the first analog signal input circuit at the same time. an inverting means for inverting the polarity of the analog signal;
and a second analog signal input circuit equipped with an adding means for adding and outputting the maximum value of the analog values that can be input to the A/D converter, and the outputs of both analog signal input circuits are respectively input to the A/D converter. Separately, convert it into a digital value, and if the digital value corresponding to the first analog signal input circuit among the digital values is smaller than the maximum convertible value of the A/D converter, the first analog signal input circuit A digital value is set in the lower bit of the digital value corresponding to the set bit, and O is set in the bit 1 bit higher than the set bit of the digital value. Among the digital values, if the digital value corresponding to the first analog signal input circuit is the maximum value that can be converted by the A/D converter, the second
The digital value corresponding to the analog signal input circuit is set in the lower bit, and the bit one bit higher than the set bit of the digital value is set to 1, and the digital value is adopted as the A/D conversion value.

Further, the invention according to claim 2 provides an A/
a D converter, a first analog signal input circuit that inputs and outputs an analog signal up to twice the maximum value of analog signals that can be input to the A/D converter, and the first analog signal input circuit. inverting means for inverting the polarity of the analog signals by simultaneously inputting them to the analog signals;
a second analog signal input circuit comprising an adding means for adding and outputting the maximum value of analog values that can be input to the A/D converter to the output of the inverting means; A third circuit that simultaneously inputs the analog signal input to the second analog signal input circuit and outputs an analog signal converted to 1/2.
The outputs of the first to third analog signal input circuits are individually converted into digital values by the A/D converter, and among the converted digital values, the first analog signal is If the digital value corresponding to the input circuit is less than 1/2 of the maximum convertible value of the A/D converter, the digital value of the first analog signal input circuit is set to the lower bit, and the digital value is A digital value in which O is set in the bit one bit higher than the set bit is adopted as an A/D conversion value, and among the digital values converted by the A/D converter, the digital value corresponds to the first analog signal input circuit. If exceeds 1/2 of the maximum convertible value of the A/D converter, the converted digital value corresponding to the second analog signal input circuit is set to the lower bit, and one bit higher than the set bit of the digital value is set. The digital value with the bit set to 1 is used as the A/D conversion value.

[Operation] Thus, the A/D conversion unit of the present invention can obtain an A/D conversion resolution that is one bit higher than the number of bits of the digital value obtained by conversion by the A/D converter used. Therefore, changes in the input analog amount can be captured in the CPU unit of the sequencer more precisely and with less error.
Sigence control will be possible.

[Example] The present invention will be explained below with reference to Examples.

FIG. 1 shows a circuit according to an embodiment of the present invention, in which the signal input channels CHO and CH are conventional analog signal input circuits 2o.

2I, and the analog signal input circuit 21 of the signal input channel CH has a jumper switch J P .

The A terminal side is turned on and the range is set to 0 to 5v.

Analog signal input circuit 22 of signal input channel CH2
As shown in the diagram, turn on the A terminal side of the jumper switch JPo and set it to the O to 5■ range, and then insert the 2-pole interlocking jumper switch JP between the resistor R and the input of the operational amplifier 3z. , this jumper switch JP,
When switched to the A terminal side, the analog input is connected to the inverting input terminal, and the power supply voltage is connected to the non-inverting input terminal, and conversely, when switched to the B terminal side, the operational amplifier 32
The analog input is connected to the non-inverting input terminal of the operational amplifier 3□, and the analog input is separated from the inverting input terminal of the operational amplifier 3□. Also, the output of operational amplifier 3 and A/
There is a jumper switch J between the input of the D converter.
P s is inserted and this jumper switch JP, A
When connected to the terminal side, the output of the operational amplifier 32 is sent to the analog signal input circuit 2 of the input signal channel CH, and when connected to the B terminal side, the output of the operational amplifier 32 is sent to the analog signal input circuit 2 of the input signal channel CH. The signal is sent to the input terminal 12.

On the other hand, analog signal input circuit 2. A two-pole interlocking jumper switch JP2 is installed between the three operational amplifiers and the resistor R9.
is inserted, and when this jumper switch JP2 is switched to the A terminal side, the output of the operational amplifier 32 of the analog signal input circuit 22 is added to the voltage from the reference power supply IC5, and the operational amplifier 3. When connected to the inverting input terminal of the operational amplifier 3. and vice versa, when switched to the B terminal side, the operational amplifier 3. The non-inverting input terminal of the analog input circuit 2. The analog input from the input terminal I of the operational amplifier 3j is connected, and the input to be added is separated from the inverting input terminal of the operational amplifier 3j. In the figure, resistors R4 and R7 and R12 and R13 are of equal value, and resistors R6 to R1+
also use the same value.

The variable resistor VR is used to adjust the output voltage of the reference power supply IC5 to approximately 5.000V, and the accuracy of the 5V obtained here is determined by the analog signal input circuit 21.
The condition is that it is made with an error smaller than the error that occurs in .

Then, by switching the jumper switches JP, ~JP 3 to the A terminal side, the resolution is set to 9 bits.
One analog signal input circuit constituting the /D conversion unit can be configured by analog signal input circuits 22 and 23,
Conversely, by switching to the B terminal side, each analog signal input circuit 22.2 can be operated independently as in the conventional case.

When converting analog signals in the 0 to IOV range to digital, use the jumper switch JP,
~JP3 is switched to the A terminal side, and the analog signal input circuit 2 of the signal input channel CH, CH2 is set to the O~5■ range by the jumper switch JP.
1. Input the same analog signals mentioned above to 2□ at the same time,
By executing the sequence program shown in FIG. 2 on a sequencer, it is possible to capture digital data with a resolution of 9 bits.

On the sequencer side, the digital value obtained by converting the analog signal output from the analog signal input circuit 21 corresponding to the signal input channel CH through the bus I/F circuit 4 and the analog signal input circuit 2 of the signal input channel CH. ．． A digital value obtained by converting an analog signal output from the A/D converter 1 is read out from the A/D converter 1 and set in a data memory (not shown). It is determined whether the digital value corresponding to channel CH among the set digital values is smaller than 255, and if it is, the final conversion value is prepared as one of the areas of the data memory of the sequencer shown in Fig. 3. Set area 88 to θ. Then, the converted digital value of signal person Kachanne CH, is placed in the final converted value area Be below 88.
~ Set to B7.

The digital value corresponding to signal input channel CH is 25.
If not smaller than 5, B in the final conversion value area
Set 8 to 1. and signal input channel CH3
The digital value corresponding to BO in the final conversion value area
~ Set to B7.

In this way, in this embodiment, the first analog signal input circuit is 2. and 2 as the second analog signal input circuit.
2. By using the circuit formed by the 23 combinations, the A/D conversion resolution by the 8-bit A/D converter 1 is increased to 9-bit resolution and the 9-bit digital value is provided to the sequencer CPU. It is possible.

By the way, using the same circuit as the circuit in Fig. 1, and using the analog signal input circuit 2° of the signal input channel CH as the third analog signal input circuit with its range set to the O to IOV range, this signal input The converted digital value of channel CH can also be used to provide 9-bit resolution.

In this case, the ranges of the signal input channels CH, , CH, are set to the 0 to 5■ range as in the above embodiment, and the jumper switches J P + to J P 3 of the signal input channels CH2 and CH1 are set to A. It is connected to the terminal side, and processing based on the flowchart shown in FIG. 4 is performed. In other words, on the CPU side of the sequencer, the signal input channel CH
o, CH,, C) l 3 analog signal input circuit 2゜,
The digital values obtained by converting the analog signals from 2+ and 2* are sent to the A/D converter 1 through the bus ■/F circuit 6.
from to data memory 1. Then, it is determined whether the digital value corresponding to the signal person channel CH, is 127 or less, and if the determination is 127 or less, the third
B8 of the final conversion value area prepared as one of the areas of the data memory of the sequencer shown in the figure is set to O. Then, the corresponding digital values of the signal input channel CH are also set in the final conversion value areas BO to B7.

The converted digital value of signal input channel CH+ is 1
If it is larger than 27, B8 of the final conversion value area
Set to 1. Then, the converted digital value of the signal input channel CH, is set to Bt in the final conversion value area.
Set to 3-B7.

In this way, in this embodiment as well, the 8-bit A/D converter 1
can be used to provide a digital value with 9-bit resolution to the sequencer's CPU.

[Effect of the invention] Since the A/D conversion unit of the present invention is configured as described above, the number of bits of the digital value obtained by conversion by the A/D converter used is increased by 1 bit. A/D conversion resolution can be obtained, and as a result, changes in the input analog amount can be
This has the advantage that it can be imported into the CPU unit of the sequencer and controlled more precisely and with less error.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of the present invention, FIG. 2 is a flowchart for explaining the operation of the embodiment of the invention as claimed in claim 1, FIG. 3 is a configuration diagram of the final conversion value area of the same, and FIG. 4 is the claim FIG. 5 is a circuit configuration diagram of a conventional example, and FIGS. 6(a) and 6(b) are diagrams for explaining range setting. 1 is an A/D converter, 2° to 2. is an analog signal input circuit, 32, 3. is an operational amplifier, 5 is a reference power supply ICl3
is a bus I/F circuit, and JP, to JPz are jumper switches. Agent Patent Attorney Ishi 1) Chief 7 Figure 2 Figure 3 Figure 4 Procedural amendments voluntarily) August 30, 1991

Claims (2)

[Claims] (1) An A/D converter that inputs a plurality of analog signals separately and converts each into a digital value of a certain number of bits;
The first input converter inputs and outputs an analog signal up to twice the maximum value of the analog signal that can be input to the A/D converter.
an analog signal input circuit, an inverting means for simultaneously inputting an analog signal input to the first analog signal input circuit and inverting the polarity of the analog signal, and an input to the output of the inverting means to the A/D converter. and a second analog signal input circuit equipped with an adding means for adding and outputting the maximum value of possible analog values, and converting the outputs of both analog signal input circuits into digital values separately by the A/D converter. However, if the digital value corresponding to the first analog signal input circuit among the digital values is smaller than the maximum convertible value of the A/D converter, the digital value corresponding to the first analog signal input circuit is smaller than the maximum convertible value of the A/D converter. A digital value in which the value is set in the lower bit and 0 is set in the bit 1 bit higher than the set bit of the digital value is adopted as the A/D conversion value, and among the digital values converted by the above A/D converter. If the digital value corresponding to the first analog signal input circuit is the maximum convertible value of the A/D converter, the digital value corresponding to the second analog signal input circuit is set to the lower bit, and the digital value is An A/D conversion unit characterized in that a digital value in which a bit one bit higher than a set bit is set to 1 is used as an A/D conversion value. (2) An A/D converter that inputs multiple analog signals separately and converts each into a digital value of a certain number of bits; a first analog signal input circuit that inputs and outputs an analog signal; an inverter that simultaneously inputs the analog signal input to the first analog signal input circuit and inverts the polarity of the analog signal; and the inverter. a second analog signal input circuit comprising an adding means for adding and outputting the maximum value of inputtable analog values of the A/D converter to the output of the A/D converter; and a third analog signal input circuit that simultaneously inputs input analog signals and outputs an analog signal converted to 1/2, and outputs from the first to third analog signal input circuits to the A/D converter. If the digital value corresponding to the first analog signal input circuit among the converted digital values is 1/2 or less of the maximum convertible value of the A/D converter, 1st above
The digital value of the analog signal input circuit is set to the lower bit, and the bit 1 bit higher than the set bit of the digital value is set to 0.The digital value is adopted as the A/D conversion value, and converted by the A/D converter. Among the converted digital values, if the digital value corresponding to the first analog signal input circuit exceeds 1/2 of the maximum convertible value of the A/D converter, the conversion corresponding to the second analog signal input circuit is performed. An A/D conversion unit characterized in that a digital value is set in a lower bit, and a bit 1 bit higher than the set bit of the digital value is set to 1, and a digital value is used as an A/D conversion value.