JPH045651U - - Google Patents
Info
- Publication number
- JPH045651U JPH045651U JP1990045838U JP4583890U JPH045651U JP H045651 U JPH045651 U JP H045651U JP 1990045838 U JP1990045838 U JP 1990045838U JP 4583890 U JP4583890 U JP 4583890U JP H045651 U JPH045651 U JP H045651U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- insulating base
- semiconductor device
- package
- lid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Die Bonding (AREA)
Description
第１図は本考案にかかる半導体素子収納用パツ
ケージの一実施例を示す断面図である。
１……絶縁基体、１ａ……凹部、１ｂ……側壁
面、２……蓋体、５……接着剤、６……メタライ
ズ金属層。
FIG. 1 is a sectional view showing an embodiment of a package for housing semiconductor elements according to the present invention. DESCRIPTION OF SYMBOLS 1... Insulating base, 1a... Recess, 1b... Side wall surface, 2... Lid, 5... Adhesive, 6... Metallized metal layer.
Claims (1)
基体と蓋体とから成る半導体素子収納用パツケー
ジにおいて、前記絶縁基体の凹部側壁面の表面粗
さを中心線平均粗さＲａで４．０乃至６０．０μ
ｍとしたことを特徴とする半導体素子収納用パツ
ケージ。 In a semiconductor device housing package comprising an insulating base having a recess for accommodating a semiconductor device and a lid, the surface roughness of the side wall surface of the recess of the insulating base is 4.0 to 60. 0μ
A package for storing semiconductor elements, characterized by the following: m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990045838U JPH045651U (en) | 1990-04-27 | 1990-04-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990045838U JPH045651U (en) | 1990-04-27 | 1990-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH045651U true JPH045651U (en) | 1992-01-20 |
Family
ID=31560371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990045838U Pending JPH045651U (en) | 1990-04-27 | 1990-04-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH045651U (en) |
-
1990
- 1990-04-27 JP JP1990045838U patent/JPH045651U/ja active Pending
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