JPH0363945U - - Google Patents
Info
- Publication number
- JPH0363945U JPH0363945U JP1989125455U JP12545589U JPH0363945U JP H0363945 U JPH0363945 U JP H0363945U JP 1989125455 U JP1989125455 U JP 1989125455U JP 12545589 U JP12545589 U JP 12545589U JP H0363945 U JPH0363945 U JP H0363945U
- Authority
- JP
- Japan
- Prior art keywords
- insulating base
- package
- recess
- semiconductor element
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Die Bonding (AREA)
Description
第1図は本考案の半導体素子収納用パツケージ
の一実施例を示す断面図、第2図は従来の半導体
素子収納用パツケージの断面図である。
1……絶縁基体、1a……凹部、1b……絶縁
膜、2……蓋体、4……接着剤。
FIG. 1 is a cross-sectional view showing an embodiment of a package for housing semiconductor elements of the present invention, and FIG. 2 is a cross-sectional view of a conventional package for housing semiconductor elements. DESCRIPTION OF SYMBOLS 1... Insulating base, 1a... Recess, 1b... Insulating film, 2... Lid, 4... Adhesive.
Claims (1)
絶縁基体と蓋体とから成る半導体素子収納用パツ
ケージにおいて、前記絶縁基体の凹部底面に該絶
縁基体と実質的に同一の熱膨張係数を有し、且つ
表面の中心線平均粗さ(Ra)がRa≧0.7μ
mである厚膜形成技術により形成される絶縁膜を
被着させたことを特徴とする半導体素子収納用パ
ツケージ。 In a package for storing a semiconductor element, which includes an insulating base and a lid having a recess for mounting and accommodating a semiconductor element, the bottom surface of the recess of the insulating base has substantially the same coefficient of thermal expansion as that of the insulating base; And the center line average roughness (Ra) of the surface is Ra≧0.7μ
1. A package for housing a semiconductor device, characterized in that it is coated with an insulating film formed by a thick film forming technique of m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989125455U JPH0723965Y2 (en) | 1989-10-26 | 1989-10-26 | Package for storing semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989125455U JPH0723965Y2 (en) | 1989-10-26 | 1989-10-26 | Package for storing semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0363945U true JPH0363945U (en) | 1991-06-21 |
| JPH0723965Y2 JPH0723965Y2 (en) | 1995-05-31 |
Family
ID=31673325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989125455U Expired - Lifetime JPH0723965Y2 (en) | 1989-10-26 | 1989-10-26 | Package for storing semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0723965Y2 (en) |
-
1989
- 1989-10-26 JP JP1989125455U patent/JPH0723965Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0723965Y2 (en) | 1995-05-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |