JPH0458536A - Semiconductor integrated circuit and its manufacturing method - Google Patents
Semiconductor integrated circuit and its manufacturing methodInfo
- Publication number
- JPH0458536A JPH0458536A JP2171521A JP17152190A JPH0458536A JP H0458536 A JPH0458536 A JP H0458536A JP 2171521 A JP2171521 A JP 2171521A JP 17152190 A JP17152190 A JP 17152190A JP H0458536 A JPH0458536 A JP H0458536A
- Authority
- JP
- Japan
- Prior art keywords
- base region
- transistor
- region
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 238000002955 isolation Methods 0.000 abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000238557 Decapoda Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はＩｃｍａｘと耐圧とｈＦｚとを全て満足し得る
トランジスタを具備する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor integrated circuit equipped with a transistor that can satisfy all of Icmax, breakdown voltage, and hFz.
く口）従来の技術
半導体集積回路では各拡散領域を共通に用いて工程を簡
略化すること、が基本的な技術思想であるので、各回路
素子は全て共通の拡散領域で構成きれ、同一チップ上の
素子（ＮＰＮ）ランシスタ）は全て同一の特性を有して
いた。(Example) Conventional technology In semiconductor integrated circuits, the basic technical idea is to use each diffusion region in common to simplify the process. The above devices (NPN rancistors) all had the same characteristics.
ところが、民生用、特に音響用ＩＣ等では、各種信号処
理用回路と同時に出力段のパワー系トランジスタが組み
込まれることが多く、回路的な要求から前記信号処理用
の小信号トランジスタと前記出力段用の大信号トランジ
スタとで電流増幅率ｈ□を異ならしめる要求がある。つ
まり、小信号トランジスタのｈＦｚを１００〜２００と
した時に、大信号トランジスタのｈ□を５０程度に下げ
て最大コレクタ電流Ｉｃ＋ｎａｘを増大するという要求
である。However, in consumer ICs, especially audio ICs, output stage power transistors are often incorporated at the same time as various signal processing circuits, and due to circuit requirements, the small signal transistors for signal processing and the output stage There is a demand for making the current amplification factor h□ different between the large signal transistor and the large signal transistor. In other words, when the hFz of the small signal transistor is set to 100 to 200, the requirement is to lower h□ of the large signal transistor to about 50 and increase the maximum collector current Ic+nax.
このようにｈ□を変更する手段として、例えば特開昭６
０−７０７５６号公報に記載されているようにベース領
域を個々に別形成する手段がある。As a means of changing h□ in this way, for example,
As described in Japanese Patent No. 0-70756, there is a method of forming base regions individually.
即ち第３図に示す如く、エピタキシャル層（１）を分離
領域（２）で分離した各アイランド（３）に、小信号ト
ランジスタ（４）用のベース領域（５）と大信号トラン
ジスタ（６）用のベース領域（７）とを個々に形成する
ものである。この時、大信号トランジスタ（６）のベー
ス領域（７）は２つの手法が考えられる。That is, as shown in FIG. 3, each island (3) in which the epitaxial layer (1) is separated by an isolation region (2) has a base region (5) for a small signal transistor (4) and a base region (5) for a large signal transistor (6). The base region (7) of the base region (7) is formed individually. At this time, two methods can be considered for the base region (7) of the large signal transistor (6).
１つは不純物濃度を高く設定してｈＦｏを小さくする手
法（第４図第１案）、２つは拡散深さを深くして（ベー
ス幅を広げる）ｈＦｌ！を手許くする手法（第４図第２
案）である。One is to set the impurity concentration high to reduce hFo (Fig. 4, first plan), and the other is to deepen the diffusion depth (widen the base width) to reduce hFl! (Fig. 4, No. 2)
draft).
（ハ）発明が解決しようとする課題
しかしながら、上記先の手法はシリコン結晶に対するポ
ロンの飽和限界があるためにそれ程高くはできず、従っ
てｈｐｐを下げるにも限界があるという欠点があった。(c) Problems to be Solved by the Invention However, the above-mentioned method has the disadvantage that it cannot be made that high because of the saturation limit of poron in silicon crystals, and therefore there is a limit to lowering hpp.
しかもツェナ降伏による耐圧劣化が危惧きれる他、ベー
ス領域（７）をイオン注入で形成する場合はドーズ量が
増す分処理時間が長くなって工程の煩雑化を招く。他方
、後の手法はｈ□を下げるという目的には合致するが、
不純物濃度と拡散深さとは密接な関係があり、ベースの
不純物濃度が低下して伝導度変調をきたすので、Ｉｃｍ
ａｘが増大しないという欠点があった。このことから、
ｈ□が同じであればベースの濃度は高い方がＩｃｍａｘ
を大きくできるのである。そして、不純物濃度とベース
幅の両者を制御したとしても、ｈＦｔとＩｃｍａｘの両
者を満足させることはやはり困難であった。In addition, there is a risk of breakdown voltage deterioration due to Zener breakdown, and when the base region (7) is formed by ion implantation, the processing time increases due to the increased dose, resulting in a complicated process. On the other hand, although the latter method meets the objective of lowering h□,
There is a close relationship between impurity concentration and diffusion depth, and as the impurity concentration in the base decreases, causing conductivity modulation, Icm
There was a drawback that ax was not increased. From this,
If h□ is the same, the higher the base concentration, the higher the Icmax.
can be made larger. Even if both the impurity concentration and base width were controlled, it was still difficult to satisfy both hFt and Icmax.
（ニ）課題を解決するための手段
本発明は上記従来の欠点に鑑み成され、比較的高い不純
物濃度を有するベース領域（２１）の底部に、ベース領
域（２１）よりは低い不純物濃度を有する低濃度ベース
領域（２３）を形成することにより、適切なｈ□を有し
且つＩｃｍａｘが大きいパワートランジスタを具備する
半導体集積回路を提供するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional drawbacks, and the bottom of the base region (21) having a relatively high impurity concentration has an impurity concentration lower than that of the base region (21). By forming the low concentration base region (23), a semiconductor integrated circuit having a power transistor having an appropriate h□ and a large Icmax is provided.
（ホ）作用
本発明によれは、低濃度ベース領域（２３）を重畳した
ことによって大信号トランジスタ（２０〉のベース幅が
広がるので、そのｈ□を小信号トランジスタ（１６）の
ｈｙｉより小びく且つ適切な値にコントロールすること
ができる。また、ベースの一部を形成するベース領域（
２１）が比較的高い不純物濃度を有するので、最大コレ
クタ電ｉＩｃｍａｘを大きくできる。(E) Effect According to the present invention, the base width of the large signal transistor (20) is expanded by overlapping the low concentration base region (23), so that its h□ is smaller than the hyi of the small signal transistor (16). In addition, the base area (which forms part of the base) can be controlled to an appropriate value.
21) has a relatively high impurity concentration, the maximum collector electric current iIcmax can be increased.
くべ〉実施例
以下に本発明の一実施例を図面を参照しながら詳細に説
明する。EXAMPLE An example of the present invention will be described below in detail with reference to the drawings.
第１図は本発明による半導体集積回路を示す断面図であ
る。同図において、（１１）はＰ型シリコン単結晶基板
、（１２）は基板（１１）表面にエビ成長して形成した
Ｎ−型エピタキシャル層、（１３〉はＮ＋型埋め込み層
、（１４）は埋め込み層（１３〉を囲みエピタキシャル
層（１２）を貫通するＰ＋型分離領域、（１５）は分離
領域（１４）によって個々に分離跡れたアイランドであ
る。FIG. 1 is a sectional view showing a semiconductor integrated circuit according to the present invention. In the figure, (11) is a P-type silicon single crystal substrate, (12) is an N-type epitaxial layer formed by shrimp growth on the surface of the substrate (11), (13> is an N+-type buried layer, and (14) is P+ type isolation regions surrounding the buried layer (13) and penetrating the epitaxial layer (12), (15) are islands separated individually by the isolation regions (14).
アイランド（１５）の１つには小信号トランジスタ（１
６）を形成すべくＰ型のベース領域（１７）とＮ＋型の
エミッタ領域（１８）を形成し、アイランド（１５）を
コレクタとして縦型ＮＰＮ ｌ−ランジスタを形成する
。＜１９）ハＮ”ｆｆコレクタコンタクト領域である。One of the islands (15) has a small signal transistor (1
6), a P type base region (17) and an N+ type emitter region (18) are formed, and a vertical NPN l- transistor is formed with the island (15) as a collector. <19) C N”ff collector contact region.
他方のアイランド〈１５）には大信号トランジスタ（２
０）を形成すべくＰ型ベース領域（２１）とＮ“型エミ
ッタ領域（２２〉を形成する他、ベース領域り２１）に
重ねてＰ−型の低濃度ベース領域（２３）を形成した。The other island (15) has a large signal transistor (2
In addition to forming a P-type base region (21) and an N"-type emitter region (22) to form a P-type base region (21), a P-type low concentration base region (23) was formed to overlap the base region (21).
（２４）ハＮ”型コレクタコンタクト領域、（２５）は
シリコン酸化膜、（２６）は各電極である。ベース領域
（２１）とエミッタ領域り２２〉は夫々共通の工程で形
成した。(24) is a N'' type collector contact region, (25) is a silicon oxide film, and (26) is each electrode. The base region (21) and the emitter region (22) were formed in a common process.
低濃度ベース領域（２３）は、ベース領域（２１〉が表
面濃度１０ ”ａｔｏｍｓｃｍ−”、拡散深ａ１．０〜
１．５μに形成されるのに対し、表面濃度１０１′〜１
０ ” ａｔｏｍｓｃｍ −’、拡散深さ２．０〜３．
０μとベース領域（２２）より低不純物濃度で深く形成
する。このように不純物濃度を低くした場合、不純物の
表面デプリートによるリークｘｆｉＥの増大が危惧され
るので、低濃度ベース領域（２３）はベース領域（２１
）をはみ出きないように形成した。The base region (21) of the low concentration base region (23) has a surface concentration of 10 "atomscm-" and a diffusion depth of a 1.0~.
1.5μ, while the surface concentration is 101′~1
0” atomscm −’, diffusion depth 2.0-3.
0μ and is formed deeper than the base region (22) with a lower impurity concentration. When the impurity concentration is lowered in this way, there is a concern that the leakage xfiE will increase due to surface depletion of impurities, so the low concentration base region (23) is
) was formed so that it did not protrude.
エミッタ領域（２２〉の下部にベース領域（２１）と低
濃度ベース領域（２３）とを二重に形成した結果、その
濃度プロファイルは第５図に示す分布となる。As a result of forming the base region (21) and the low concentration base region (23) in double form under the emitter region (22), the concentration profile becomes the distribution shown in FIG.
即ち、比較的高不純物濃度のベース領域（２１）が形成
する比較的急峻な傾きと、比較的低不純物濃度の低濃度
ベース領域（２３）が形成する緩やかな傾きとの２段階
の傾きを有する。すると、大信号トランジスタ（２０）
のベース幅ＷＢは同図に示す如く低濃度ベース領域（２
３）の拡散深さで決まるので、ベース領域（１７）だけ
の小信号トランジスタ（１６）よりはベース幅を犬にで
き、電流増幅率ｈＦ、を小にできる。低不純物濃度の領
域であるから、ｈＦｔが下がり過ぎるということも無い
。と同時に、大信号トランジスタ（２０）のベースには
ベース拡散による比較的高不純物濃度のベース領域（２
１）が重なるので、ベースの伝導度変調による影響が少
なく、従ってｈｙｚを下げたことにより得られるＩｃｍ
ａｘの増大を最大限有効に引き出すことができる。That is, it has two slopes: a relatively steep slope formed by the base region (21) with a relatively high impurity concentration, and a gentle slope formed by the low concentration base region (23) with a relatively low impurity concentration. . Then, large signal transistor (20)
The base width WB of the low concentration base region (2
Since it is determined by the diffusion depth (3), the base width can be made smaller than that of the small signal transistor (16) having only the base region (17), and the current amplification factor hF can be made smaller. Since this is a low impurity concentration region, hFt does not drop too much. At the same time, a base region (2) with relatively high impurity concentration due to base diffusion is formed in the base of the large signal transistor (20).
1) overlaps, there is less influence from conductivity modulation of the base, and therefore the Icm obtained by lowering hyz
It is possible to maximize the increase in ax.
第２図Ａ乃至第２図りは本願集積回路の製造方法を示し
た。FIGS. 2A to 2D illustrate a method of manufacturing the integrated circuit of the present invention.
先ず第２図Ａに示す如く埋め込み層（１３）と下側の分
離領域（１４）を形成した基板（１１）上にエピタキシ
ャル層（１２）を形成し、低濃度ベース領域（２３〉に
対応する部分に選択的にポロン（Ｂ）を必要なトス量だ
けイオン注入し、
第２図Ｂに示す通り基板（１１）全体に熱処理を加える
ことによりエピタキシャル層（１２）表面にドープした
ボロン（Ｂ）を所望深きまでドライブインをし、
第２図Ｃに示す通り上側の分離領域（１４）を形成した
後、再びボロン（Ｂ）を選択的にイオン注入してドライ
ブインすることにより小信号トランジスタ（１６）のベ
ース領域（１７）と大信号トランジスタ（２０）のベー
ス領域（２１）を同時形成し、そして第２図りに示す通
りエミッタ拡散でエミッタ領域（１８）（２２）を形成
することにより小信号トランジスタ（１６）と大信号ト
ランジスタ（２０）を形成する。First, as shown in FIG. 2A, an epitaxial layer (12) is formed on a substrate (11) on which a buried layer (13) and a lower isolation region (14) are formed, and corresponds to the low concentration base region (23). Boron (B) doped onto the surface of the epitaxial layer (12) by selectively implanting boron (B) in the required amount and heat-treating the entire substrate (11) as shown in Figure 2B. After driving in to a desired depth and forming an upper isolation region (14) as shown in FIG. 2C, boron (B) is selectively implanted and driven in again to form a small signal transistor ( 16) and the base region (21) of the large signal transistor (20) are simultaneously formed, and the emitter regions (18) and (22) are formed by emitter diffusion as shown in the second diagram. A signal transistor (16) and a large signal transistor (20) are formed.
本願構成は、多少の熱処理を加えても拡散深きが変動し
にくい、拡散済みの低濃度ベース領域（２３）にベース
拡散を処して小信号トランジスタ（１６〉と大信号トラ
ンジスタ（２０）を形成するので、ベース拡散は小信号
トランジスタ（１６）用に制御して拡散を行うことがで
きる。従って、小信号トランジスタ（１６）、大信号ト
ランジスタ（２０）共に特性の制御が極めて容易である
。In the configuration of the present application, a small signal transistor (16) and a large signal transistor (20) are formed by subjecting the diffused low concentration base region (23) to base diffusion, where the diffusion depth does not easily change even if a certain amount of heat treatment is applied. Therefore, the base diffusion can be controlled and diffused for the small signal transistor (16).Therefore, it is extremely easy to control the characteristics of both the small signal transistor (16) and the large signal transistor (20).
（ト）発明の効果
以上に説明した通り、本発明によれば、大信号トランジ
スタ（２０）に低濃度ベース領域（２３）を重ねること
によって、ｈ、２が高い小信号トランジスタ（１６）と
ｈＦ！が小さい大信号トランジスタ（２０）とを容易に
共存できる利点を有する。また、大信号トランジスタ（
２０）のベースは比較的高い不純物濃度を有するベース
領域（２１）との重畳であるから、伝導度変調によるＩ
ｃｍａｘの低下が少なく、従ってＩＣｍａｘを最大限に
増大できる利点を有する。きらに、大信号トランジスタ
（２０）のｈ□を下げることによってＡＳＯを増大せし
め、出力段トランジスタとして適切な特性に製造できる
利点をも有する。そして更に、低濃度ベース領域（２３
）を利用することによって、大信号、小信号共に特性の
制御が容易であるという利点をも有する。(G) Effects of the Invention As explained above, according to the present invention, by overlapping the low concentration base region (23) on the large signal transistor (20), the small signal transistor (16) with high h,2 and hF ! It has the advantage that it can easily coexist with the small large signal transistor (20). In addition, large signal transistors (
Since the base of 20) is overlapped with the base region (21) having a relatively high impurity concentration, the I
This has the advantage that the decrease in cmax is small and therefore ICmax can be increased to the maximum. In addition, it has the advantage that the ASO can be increased by lowering the h□ of the large signal transistor (20), and it can be manufactured to have characteristics suitable for an output stage transistor. Furthermore, a low concentration base region (23
) has the advantage that the characteristics of both large and small signals can be easily controlled.
第１図は本発明を説明するだめの断面図、第２図Ａ−Ｄ
はその製造方法を説明するための断面図、第３図は従来
例を説明するための断面図、第４図は従来の不純物濃度
分布を示す図、第５図は本願の不純物濃度分布を示す図
である。
第３図
第４図
第５図
←Ｗ８゜Fig. 1 is a sectional view of a tank for explaining the present invention, Fig. 2 A-D
3 is a sectional view for explaining the manufacturing method, FIG. 3 is a sectional view for explaining the conventional example, FIG. 4 is a diagram showing the conventional impurity concentration distribution, and FIG. 5 is the impurity concentration distribution of the present application. It is a diagram. Figure 3 Figure 4 Figure 5 ←W8゜
Claims (7)
ース領域とエミッタ領域を重ねて形成した縦型トランジ
スタを具備する半導体集積回路において、 前記エミッタ領域下部のベース領域の不純物プロファイ
ルが、前記エミッタ領域の全面において、急峻な傾きを
有する第１の勾配と、該第１の勾配より緩やかな傾きを
有する第２の勾配との、２段階の勾配を有することを特
徴とする半導体集積回路。(1) In a semiconductor integrated circuit including a vertical transistor in which a base region and an emitter region are formed on one surface of an electrically isolated island, the impurity profile of the base region below the emitter region is different from the impurity profile of the base region below the emitter region. 1. A semiconductor integrated circuit having two gradients over the entire region: a first gradient having a steep gradient and a second gradient having a gentler gradient than the first gradient.
ース領域とエミッタ領域を重ねて形成した縦型トランジ
スタを具備する半導体集積回路において、 前記ベース領域の下部に前記エミッタ領域の全面に対応
する部分に前記ベース領域よりは低不純物濃度の低濃度
ベース領域を有することを特徴とする半導体集積回路。(2) In a semiconductor integrated circuit comprising a vertical transistor in which a base region and an emitter region are formed by overlapping each other on one surface of an electrically isolated island, a lower part of the base region corresponds to the entire surface of the emitter region. A semiconductor integrated circuit characterized in that a portion thereof has a low concentration base region having a lower impurity concentration than the base region.
エピタキシャル層と、 前記エピタキシャル層を分離して形成した複数個のアイ
ランドと、 第１のトランジスタを構成するために、前記アイランド
の１つの表面に形成した一導電型のベース領域およびベ
ース領域表面に形成した逆導電型のエミッタ領域と、 第２のトランジスタを構成するために、前記アイランド
の他の１つの表面に形成した一導電型のベース領域およ
び逆導電型のエミッタ領域と、前記第２のトランジスタ
のベース領域に重ねて形成した前記ベース領域より深く
且つ前記ベース領域よりは低不純物濃度の低濃度ベース
領域とを具備することを特徴とする半導体集積回路。(3) an epitaxial layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type; a plurality of islands formed by separating the epitaxial layer; A base region of one conductivity type formed on one surface, an emitter region of opposite conductivity type formed on the surface of the base region, and one conductivity type formed on the other surface of the island to constitute a second transistor. and a low concentration base region formed over the base region of the second transistor, which is deeper than the base region and has a lower impurity concentration than the base region. A semiconductor integrated circuit characterized by:
のトランジスタのベース領域とを同時形成したことを特
徴とする請求項第３項に記載の半導体集積回路。(4) The base region of the first transistor and the second transistor
4. The semiconductor integrated circuit according to claim 3, wherein the base region of the transistor is formed at the same time as the base region of the transistor.
して構成したことを特徴とする請求項第３項に記載の半
導体集積回路。(5) The semiconductor integrated circuit according to claim 3, wherein the second transistor is configured as an output transistor.
度ベース領域を完全に覆うように重畳することを特徴と
する請求項第１項に記載の半導体集積回路。(6) The semiconductor integrated circuit according to claim 1, wherein the base region of the second transistor overlaps the low concentration base region so as to completely cover it.
ャル層を形成する工程、 前記エピタキシャル層の表面に一導電型の不純物をイオ
ン注入し、所望深さに拡散して大信号トランジスタ用の
低濃度ベース領域を形成する工程、 前記エピタキシャル層の表面に一導電型の不純物を選択
的に拡散し、小信号トランジスタ用のベース領域と前記
大信号トランジスタ用の前記低濃度ベース領域に重畳し
前記低濃度ベース領域よりは高い不純物濃度を有し且つ
前記低濃度ベース領域よりは浅いベース領域を形成する
工程、前記小信号トランジスタのベース領域の表面に逆
導電型のエミッタ領域を形成して所望のｈ＿Ｆ＿ｚを得
、且つ前記低濃度ベース領域とベース領域が重畳した部
分にも前記大信号トランジスタのエミッタ領域を形成し
て前記小信号トランジスタのｈ＿Ｆ＿ｚよりは小さいｈ
＿Ｆ＿ｚを得る工程、 とを具備することを特徴とする半導体集積回路の製造方
法。(7) Forming an epitaxial layer of opposite conductivity type on a semiconductor substrate of one conductivity type, ion-implanting an impurity of one conductivity type into the surface of the epitaxial layer and diffusing it to a desired depth to form a large signal transistor. forming a low concentration base region, selectively diffusing impurities of one conductivity type into the surface of the epitaxial layer so as to overlap the base region for the small signal transistor and the low concentration base region for the large signal transistor; forming a base region having a higher impurity concentration than the low concentration base region and being shallower than the low concentration base region; forming an emitter region of opposite conductivity type on the surface of the base region of the small signal transistor to form a desired base region; h_F_z is obtained, and an emitter region of the large signal transistor is also formed in a portion where the low concentration base region and the base region overlap, so that h_F_z is smaller than h_F_z of the small signal transistor.
A method for manufacturing a semiconductor integrated circuit, comprising: a step of obtaining _F_z.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2171521A JPH07111975B2 (en) | 1990-06-28 | 1990-06-28 | Semiconductor integrated circuit and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2171521A JPH07111975B2 (en) | 1990-06-28 | 1990-06-28 | Semiconductor integrated circuit and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0458536A true JPH0458536A (en) | 1992-02-25 |
| JPH07111975B2 JPH07111975B2 (en) | 1995-11-29 |
Family
ID=15924660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2171521A Expired - Fee Related JPH07111975B2 (en) | 1990-06-28 | 1990-06-28 | Semiconductor integrated circuit and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07111975B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227775A (en) * | 2006-02-24 | 2007-09-06 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
-
1990
- 1990-06-28 JP JP2171521A patent/JPH07111975B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227775A (en) * | 2006-02-24 | 2007-09-06 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07111975B2 (en) | 1995-11-29 |
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