JPH0459640U - - Google Patents
Info
- Publication number
- JPH0459640U JPH0459640U JP10326390U JP10326390U JPH0459640U JP H0459640 U JPH0459640 U JP H0459640U JP 10326390 U JP10326390 U JP 10326390U JP 10326390 U JP10326390 U JP 10326390U JP H0459640 U JPH0459640 U JP H0459640U
- Authority
- JP
- Japan
- Prior art keywords
- logic circuit
- program data
- forming
- common terminal
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Description
図面は本考案の一実施例を示す図である。
１……プログラマブルゲートアレイ、２……Ｅ
ＰＲＯＭ、４……共用端子、５……論理回路、７
……デコーダ。
The drawings are diagrams showing one embodiment of the present invention. 1...Programmable gate array, 2...E
PROM, 4... Common terminal, 5... Logic circuit, 7
……decoder.
Claims (1)
に応じた論理回路を形成し、該論理回路を形成す
るためのプログラムデータの入力と、形成後の前
記論理回路からの処理データの出力と、を共用し
た共用端子を有するプログラマブルゲートアレイ
において、 前記共用端子に印加されたプログラムデータの
所定ビツトをデコードし、前記論理回路を形成す
るための最終プログラムデータの所定ビツトのデ
コード出力によつて、前記論理回路から前記共用
端子への出力路を遮断状態から導通状態とさせる
デコーダを備えたことを特徴とするプログラマブ
ルゲートアレイ。 (2) 外部メモリから読み出されるプログラムデ
ータは、所定ビツトが論理回路を形成するための
論理形成データとされ、残余ビツトがデコーダで
デコーダすべきアドレスデータとされ、前記デコ
ーダが前記論理回路の形成を終了すべき最終アド
レスデータをデコードすることによつて、前記論
理回路から前記共用端子への出力路を遮断状態か
ら導通状態とさせることを特徴とする請求項(1)
記載プログラマブルゲートアレイ。[Claims for Utility Model Registration] (1) Forming a logic circuit according to program data stored in an external memory, inputting program data for forming the logic circuit, and inputting program data from the logic circuit after formation. In a programmable gate array having a common terminal that shares the output of processing data, a predetermined bit of program data applied to the common terminal is decoded, and a predetermined bit of final program data for forming the logic circuit is decoded. A programmable gate array comprising: a decoder that changes an output path from the logic circuit to the common terminal from a cutoff state to a conduction state by an output. (2) In the program data read from the external memory, predetermined bits are used as logic formation data for forming a logic circuit, remaining bits are used as address data to be decoded by a decoder, and the decoder forms the logic circuit. Claim (1) characterized in that by decoding the final address data to be terminated, an output path from the logic circuit to the common terminal is brought into a conductive state from a cut-off state.
Described programmable gate array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10326390U JPH0459640U (en) | 1990-09-28 | 1990-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10326390U JPH0459640U (en) | 1990-09-28 | 1990-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0459640U true JPH0459640U (en) | 1992-05-21 |
Family
ID=31848071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10326390U Pending JPH0459640U (en) | 1990-09-28 | 1990-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0459640U (en) |
-
1990
- 1990-09-28 JP JP10326390U patent/JPH0459640U/ja active Pending
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