JPH0459700B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a data discrimination circuit, and more particularly to a data discrimination circuit which prevents a read data phase margin from being low even when there is a large instantaneous fluctuation in data input.

PRIOR ART Generally, in high-speed magnetic disk devices, etc., a phase synchronization circuit is used to create a timing signal synchronized with read data. It has frequency follow-up characteristics for frequency fluctuations in data input caused by this, and jitter suppression characteristics for instantaneous timing fluctuations caused by pattern peak shifts, noise, and the like.

FIG. 1 is a block diagram of a well-known phase-locked circuit, including a phase comparator 20 that detects the phase difference between two signals, data input and VC output.
a low-pass wave generator 30 that smooths the output of the signal to obtain a DC output proportional to the difference between the two signals;
A voltage controlled oscillator 40 whose oscillation frequency is controlled by the DC output from the oscillator 40 generates a data discrimination window based on the VC output signal of the oscillator 40, and distinguishes between data and data (or between data and data) depending on the input timing of data input. The circuit includes a data discrimination circuit 50 for discriminating clock signals (clocks) and synchronizing data output, and a data timing correction circuit 60 for adjusting the timing of data input so that the data input is at the center of the discrimination window.

FIG. 2 shows an example of a conventional data discrimination circuit 50 in a code recording system in which there is at least one bit "0" between bits "1" and "1" in the data input, and the operation shown in FIG. An explanatory diagram is shown in FIG. The VC output signal, which has frequency tracking characteristics with respect to data input and is output from the phase synchronization circuit configured as described above, is frequency-divided by flip-flops (hereinafter referred to as "FF") 1 and 1' in the data discrimination circuit 50. , signal AB, CD,
BC and DA are generated and passed through the NAND circuit 16, NAND circuit 17 and OR circuit 8, respectively.
Generates reset signals for FF9 and FF10. Also, signals AB and CD are FF9 and FF1, respectively.
The input signal is 0, that is, the data discrimination window width _Tw .
If there is no instantaneous timing fluctuation in the data input as described above, the data timing correction circuit 60 adjusts the data input to the pulse width of the signal AB or CD as shown by the data input bit "1" in FIG.
That is, since it is the center of the data discrimination window _TW , only one of FF9 or FF10 is set by data input. That is, it is discriminated and set to either FF9 or FF10 depending on the input timing of data input. When data input “1” is set to FF9, when signal AB becomes “0”,
FF15 through NAND circuit 12 and OR circuit 14
A synchronized data output "1" set in the FF15 is obtained by the synchronized VC output signal. When data input "1" is set to FF10, when signal CD becomes "0", NAND circuit 13, OR circuit 14 and
Data output “1” synchronized through FF15
get. In Fig. 3, the period T of the VC output is
The period of data input and the signal AB and data discrimination window width T _w which is the pull-in range of data input.
Equal to the CD pulse width.

FIG. 3B shows a case where there is an instantaneous timing fluctuation in data input. If there is a small timing fluctuation such as the first and second bits "1" of the data input, a correct data output can be obtained as in case A above. However, if there is a large timing fluctuation such as the third bit "1" and the data input is input when the signals AB and CD are switched, the bit "1" of the data input and the signal AB or CD are input in FF9 and FF10. FF9
and 10 may not be set, or both may be set at the same time, resulting in incorrect data output. In other words, for a bit "1" that has an instantaneous fluctuation with a small timing with respect to the data discrimination window width _Tw , it is discriminated into data and data (data and clock in the MFM recording method), and the data is synchronized with the VC output signal. However, if the fluctuation is very large and the data input bit "1" is input within the switching time of the circuit itself, which is determined by the performance of the circuit elements of the data discriminator circuit, the above-mentioned situation will occur. This caused a problem in that the phase margin of read data decreased.

Purpose of the Invention The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in conventional data discrimination circuits, and to solve the problems even when there are large instantaneous fluctuations in data input. Another object of the present invention is to provide a data discrimination circuit that prevents the phase margin of read data from decreasing.

General Description of the Invention In order to achieve the above object, the data discriminator circuit of the present invention combines a data input and an output (fifth
A circuit (1 in Figure 5) that receives the VCO output (as shown in the figure) as an input and obtains a window for distinguishing between data and data or data and clock depending on the input timing of the data input, and sets the data discriminated by the window. a data set circuit (9, 10 in Figure 5) and a data output discriminator circuit (9, 10 in Figure 5) that synchronizes the data set in the data set circuit with the output of the phase synchronization circuit (VCO output in Figure 5) and obtains a data output. In the data discrimination circuit equipped with 11) in Fig. 5, the data discrimination window expansion circuit (2,
3) and the data output discrimination circuit (1 in Figure 5).
Means (fifth circuit) for resetting the data set circuit (9, 10 in FIG. 5) by the data output of (1)
It is characterized by having a signal line between the R terminals 15, 8 and 9, 10 in the figure.

Embodiments of the Invention Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 5 is a diagram showing a data discrimination circuit which is an embodiment of the present invention, and FIG. 6 is an explanatory diagram of its operation. The features of the circuit of this embodiment include the provision of data discrimination window expansion circuits 2 and 3 consisting of a delay circuit and an OR circuit;
and a data output discrimination circuit 11 is provided. That is, in FIG. 5, the VC output, which has a frequency tracking characteristic with respect to the data input outputted from the phase synchronization circuit, is frequency-divided by FF1 to generate signals AB and CD. These signals pass through discrimination window expansion circuits 2 and 3, which are composed of delay circuits 4 and 5 and OR circuits 6 and 7, to generate signals D0W and D1W with an expanded data discrimination window width T _W +△T _w ,
These become input signals for FF9 and FF10, respectively. The value of the delay time of delay circuits 4 and 5 is determined by the performance of FFs 9 and 10.
It is preset to T _w or a slightly larger value.

If there is no instantaneous timing fluctuation in the data input as shown in FIG. 6A, the timing correction circuit 6
Since the data input is set in advance to be at the center of the pulse width of the signal D0W or D1W by 0, only one of FF9 or FF10 is set by the data input. That is, depending on the set timing of the data input itself, it is discriminated as either FF9 or FF10. When the signal D0W is on, FF9 is set by the data input, and when the signal AB becomes "0", it becomes the input signal of the FF15 through the NAND circuit 12 and the OR circuit 14 of the data output discrimination circuit 11, and is input by the VC output signal. ,FF15
is set to obtain data output. When signal D1W is on, FF10 is set by data input, and when signal CD becomes "0", NAND circuit 1
3. Obtain data output through OR circuit 14 and FF15.

FIG. 6B shows a case where there is an instantaneous timing fluctuation in data input. If the fluctuation is a small fluctuation such as the first or second bit "1" of the data input, it is correctly discriminated as FF9 or FF10 as shown in FIG. 6A. Furthermore, the third bit of the data input power, "1", indicates the case where the fluctuation is very large, and since there is data input when both the signals D0W and D1W are "1", the FF9
and 10 are set at the same time, but the data discrimination circuit 11 obtains normal data output. That is, when the signal AB is "0", it is passed through the NAND circuit 12 and the OR circuit 14, while when the signal CD is "0", it is passed through the NAND circuit 13 and the OR circuit 14, and the signal is passed through the FF 15.
The data output is obtained by the VC output signal. After that, the data output causes FF9 to
The FF 10 is reset through the OR circuit 8.
In Figure 6, the period of data input, the period T of VC output, and the pulse width T _w of signals AB and CD.
are equal, and the expanded data discrimination window width is the pulse width T _W +ΔT _w of the signals D0W and D1W.

In the above embodiment, the FF of the data discrimination circuit
Although a D-type FF was used in the above, the present invention is not limited to this, and it goes without saying that it is also effective when using other FFs such as an RS-type FF.

Furthermore, in the above embodiment, the so-called 2-7 recording method in which there is at least one bit "0" between data input bits "1" and "1" was explained as an example. The present invention is effective even in the case of the MFM recording method, if the data input pulse width is made smaller than T/2 with respect to the data period T, as shown in FIG. In this case, the data discrimination window width
T _w =0.5T. Also, set the FF9 side to data, FF
If the FF10 side is used as a clock, it is necessary to add a circuit to prevent the output of FF10 from being treated as a data output. Furthermore, in the M ² FM recording system, the delay times of the delay circuits 4 and 5 in the data discrimination window extension circuits 2 and 3 of the embodiment circuit shown in FIG. 5 are asymmetric, for example, the delay time of the delay circuit 4 is , becomes effective by reducing the delay time of the delay circuit 5, and in this case, the data discrimination window width T _w =
It is possible to set it to 0.6T.

Effects of the Invention As described above, according to the present invention, a circuit takes data input and the output of a phase synchronized circuit as input, and obtains a window for distinguishing between data and data or data and clock depending on the input timing of the data input. In a data discrimination circuit, the data discrimination circuit includes a data set circuit for setting data discriminated by the window, and a circuit for obtaining a data output by synchronizing the data set in the data set circuit with the output of a phase synchronization circuit. The window is expanded so that a portion thereof overlaps with each other, and when one data input is set in both of two data discriminator circuits, only one of them is selected, so that large instantaneous fluctuations in the data input are avoided. This has the remarkable effect that it is possible to realize a data discrimination circuit that prevents the phase margin of read data from deteriorating even when there is a problem.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a phase-locked circuit, Figure 2 is a diagram of a conventional data discrimination circuit, Figure 3 is a diagram explaining its operation, Figure 4 is a diagram explaining the MFM recording method, and Figure 5 is a diagram of the book. FIG. 6 is a diagram showing a data discrimination circuit according to an embodiment of the invention, and is an explanatory diagram of its operation. 1, 9, 10, 15: FF, 2, 3: Data discrimination window expansion circuit, 4, 5: Delay circuit, 6, 7, 8,
14: OR circuit, 11: Data output discrimination circuit, 1
2, 13: NAND circuit, 20: Phase comparator, 3
0: Low frequency generator, 40: Voltage controlled oscillator, 50:
Data discrimination circuit, 60: Timing correction circuit.

Claims (1)

[Claims] 1 A circuit that receives data input and the output of a phase-locked circuit as input, and obtains a window for distinguishing between data and data or data and clock depending on the input timing of the data input, and a circuit that sets the data discriminated by the window. A data discrimination circuit comprising a data set circuit and a data output discrimination circuit that obtains a data output by synchronizing the data set in the data set circuit with the output of a phase synchronization circuit.
a data discrimination window expansion circuit for expanding two of the windows so that parts of the windows overlap each other; and means for resetting the data set circuit by the data output of the data output determination circuit, the data set circuit being expanded. 1. A data discrimination circuit, wherein data discriminated by a window is set, and the data output discrimination circuit discriminates the data set in the data set circuit by the window before being expanded.