JPH0459717B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gallium arsenide semiconductor memory device, and particularly to the structure of its memory cell.

[Conventional technology]

Figure 3 shows, for example, the 1981 IEDM (International
83 is a diagram showing the circuit configuration of a memory cell in a conventional gallium arsenide semiconductor memory device described on page 83 of the proceedings of the Electron Device Meeting. In this figure, 1 and 2 are normally-on type metal-semiconductor effect transistors (hereinafter, metal-semiconductor effect transistors are abbreviated as MESFET), and 3 to 6 are normally-off type MESFETs.

Normally-on type MESFET and normally-off type
MESFET3 uses normally-on type MESFET1 as a load and normally-off type MESFET3 as a driver.
The first E/D inverter circuit has an input as node 9 and an output as node 8, and is a normally-on type.
MESFET1 has a drain connected to power supply node 7, a gate and a common source, and is normally off type.
Connected to the drain of MESFET3. The gate of normally-off type MESFET 3 is connected to input node 9,
The sources are each connected to ground potential. Similarly, normally-on type MESFET2 and normally-off type MESFET4 are normally-on type MESFET2.
A second E/D inverter circuit is constructed with the normally-off type MESFET 4 as the load, the normally-off type MESFET 4 as the driver, the input as the node 8, and the output as the node 9. is commonly connected to the drain of normally-off type MESFET4. Normally-off type MESFET 4 has its gate connected to input node 8,
The sources are each connected to ground potential. Further, the inputs and outputs of the first and second E/D inverter circuits are cross-connected. Node 8 and node 9 become storage nodes where data is stored.

Further, the normally-off type MESFET 5 is a transfer gate, and is connected between the storage node 8 and the bit line 10, and its gate becomes the word line 12. Similarly, the normally-off type MESFET 6 is also a transfer gate, and is connected between the storage node 9 and the bit line 11, with its gate serving as the word line 12.

Next, the operation will be explained. When the memory cell is in a non-selected state, the word line 12 is at a low level and the transfer gates 5 and 6 are both non-conductive, so that the memory cell is separated from the bit lines 10 and 11. At this time, one pair of high and low data is held in the memory cell by the following mechanism.

First, Fig. 4 shows the above first or second E/D.
This shows the transfer characteristics of the inverter. In the figure, a solid line 18 is the transfer characteristic of the inverter, and a broken line 19 is a curve obtained by folding the solid line 18 symmetrically with respect to y=x. When the input is low level, the driver FET
becomes non-conductive, so the output is pulled to a high level by the load FET. Here, if the potential of the power supply 7 is set to 1.5V, the high level of the output will try to be raised to 1.5V, but in reality, the output is input to the gate of the other inverter, so the gate source of the driver FET Due to the presence of a parasitic shot diode formed in between, the shot barrier height is clamped at approximately _φB , and this value is normally approximately 0.6V. Next, when the input level to the inverter rises and exceeds the threshold voltage of the driver FET, the driver FET becomes conductive and normally the current drive capability of the driver FET is reduced by the load.
Since the current drive capacity is set several times higher than the current drive capacity of the FET, the output level quickly drops to low level. When the input level rises further, the output level is gradually raised due to the presence of a parasitic shotgun diode formed between the gate and drain of the driver FET. In this way, the transfer characteristic of the first or second E/D inverter when a memory cell is not selected becomes as shown by the solid line 18 in FIG. 4.

Furthermore, since the inputs and outputs of the first and second E/D inverters are cross-connected to each other, the potential of the storage nodes 8 and 9 in the non-selected state is at the intersection (stable point) A of the solid line 18 and the broken line 19. ,B
determined by That is, storage node 8,
9 holds one pair of high and low data.

Next, when the memory cell is in the selected state, the word line 12 becomes high level during reading,
Transfer gates 5 and 6 are rendered conductive and the held data is read onto bit lines 10 and 11.
The data read onto the bit line is further amplified by a subsequent circuit and output to the outside.

To write data to a memory cell, the word line 12 is set to a high level to put the memory cell in a selected state, and the bit lines 10 and 11 are also set to a high level by a write circuit, one of which is set to a high level, and the other set to a low level.
By setting the bit line to the level, the data on the bit line is written to the storage node of the memory cell.

MESFETs generally have an active region doped with impurities on a gallium arsenide semiconductor substrate, but when this active region is at a high potential, the electrons generated in the substrate by the incidence of alpha rays are collected into the active area of the Therefore, the memory cell
When α rays enter the active layer of the high-side storage node, electrons are collected, and the potential of this node decreases. The amount of this decrease is usually more than 0.6V, and therefore, due to the incidence of α rays on the High side storage node, the potential of the High side storage node becomes lower than the potential of the Low side storage node, and data is lost. A reversal occurs. This becomes unrecoverable until the next write.

Increases the resistance of memory cells to the incidence of alpha rays,
In order to reduce the probability of data inversion, the fifth
As shown in the figure, storage nodes 8, 9 and
Shortcut diodes 14, 13 between GND
One possible method is to increase the capacity of the storage nodes 8 and 9 by inserting them in the forward direction. That is, by increasing the capacitance of the storage node, the amount of change in potential for the same amount of charge collection is reduced, and the soft error rate is reduced. However, this method has the following problems. For example, in Figure 5, node 8 has a high level and node 9 has a low level.
Assuming that level data is maintained,
In addition to the short-circuit diode between the gate and source of the driver FET 4, an additional short-circuit diode 14 is connected in parallel between the storage node 8 on the High side and GND. The shot current of the diode increases and the potential of node 8 decreases. In particular, in memory cells, the current supply capacity of normally-on MESFETs 1 and 2 of the load is reduced as much as possible to reduce power consumption.
Due to the substantial increase in the area of the Schottky diode connected between GND and GND, the potential of node 8 is significantly reduced. When the potential of the high-side node 8 decreases, the voltage amplitude of data held in the memory cell decreases, so not only does the effect of reducing the soft error rate by adding the diode not increase, but the noise margin also decreases.

[Problem to be solved by the invention]

Since the memory cell in the conventional gallium arsenide semiconductor memory device has the above configuration,
The high level of data held in memory cells is
The voltage is limited to about 0.6V due to the height of the shot barrier between the gate and source of driver FET 3 or 4, and as a result, the voltage amplitude of the data held by the memory cell is small, making it easy to cause soft errors due to the incidence of alpha rays. There was a problem. Furthermore, even if it is attempted to reduce soft errors caused by α rays by adding a capacitor as shown in Figure 5, there is a problem that not only the data voltage amplitude decreases and the effect is not improved, but also the noise margin decreases. It was hot.

This invention was made to solve the above-mentioned problems, and it is possible to reduce the area on the substrate of the Schottky diode used to add capacity to a storage node, and to increase the capacity of this storage node. gallium arsenide semiconductor memory that can perform this while suppressing a decrease in the potential amplitude of the node to a small extent, thereby preventing the soft error reduction effect due to the increase in capacitance from being canceled out and the noise margin from decreasing. The purpose is to obtain equipment.

[Means for solving problems]

The gallium arsenide semiconductor memory device according to the present invention includes:
A Schottky diode is connected in the forward direction to the storage node of a memory cell to add capacitance, and the cathode potential of the added Schottky diode is set to be higher than the low potential power supply to which the memory transistor is connected. be.

[Effect]

In this invention, since the capacity is added by connecting the Schottky diode to the storage node in the forward direction, the amount of increase in capacity of the storage node by connecting the diode is greater than that by connecting the diode in the reverse direction, which reduces soft errors. The area occupied by the Schottky diode used on the substrate can be reduced. In addition, since the cathode of the Schottky diode is fixed at a potential higher than the low potential power supply of the memory transistor, the forward current of the diode that reduces the potential amplitude of the storage node is reduced, and this reduces the potential of the storage node. By suppressing the decrease in amplitude, it is possible to avoid canceling out the soft error reduction effect or reducing the noise margin due to the decrease in potential amplitude.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, 1 and 2 are normally on type
MESFET, 3 to 6 are normally off type
MESFETs 13 and 14 are shotgun diodes.

Normally-on type MESFET1 and normally-off type
MESFET3 uses normally-on type MESFET1 as a load and normally-off type MESFET3 as a driver.
The first E/D inverter circuit has an input as node 9 and an output as node 8, and is a normally-on type.
MESFET1 has a drain connected to power supply node 7, a gate and a common source, and is normally off type.
Connected to the drain of MESFET3. Further, the normally-off type MESFET 3 has its gate connected to the input node 9 and its source connected to the ground potential.
Similarly, normally-on type MESFET2 and normally-off type MESFET4 are normally-on type MESFET2 and normally-off type MESFET4.
Load MESFET2, normally-off type MESFET4
constitutes a second E/D inverter circuit with a driver as a driver, an input as a node 8, and an output as a node 9,
The drain of the normally-on type MESFET 2 is connected to the power supply node 7, and the gate and source are commonly connected to the drain of the normally-off type MESFET 4. Further, the normally-off type MESFET 4 has its gate connected to the input node 8 and its source connected to the ground potential. Furthermore, the first and second E/D
The inverter circuits have their respective inputs and outputs cross-connected. Node 8 and node 9 become storage nodes where data is stored.

Further, the normally-off type MESFET 5 is a transfer gate, and is connected between the storage node 8 and the bit line 10, and its gate becomes the word line 12. Similarly, the normally-off type MESFET 6 is also a transfer gate, and is connected between the storage node 9 and the bit line 11, with its gate serving as the word line 12.

Furthermore, the Schottky diode 13 is connected to the node 9
is used as an anode, and a cathode is connected to the power supply 15. Similarly, Schottky diode 14 has node 8 as its anode and cathode connected to power supply 15.

Next, the operation will be explained. When the memory cell is in a non-selected state, word line 12 is at a low level and transfer gates 5 and 6 are both non-conductive, so that the storage node of the memory cell is disconnected from bit lines 10 and 11. At this time,
A pair of high and low data is held in the storage node of the memory cell using the same principle as in the conventional example. In the conventional example, the addition of the Schottky diodes 13 and 14 caused a drop in the high level of the internal node due to the current flowing through these diodes, but in this embodiment, the Schottky diodes 1
Since the power supply 15 to which the cathodes 3 and 14 are connected is separated from the ground potential, by increasing the potential of the power supply 15, it is possible to prevent the high level of the internal node from decreasing. That is, in a normal shottock diode, under a bias condition of about the shottock barrier, the current increases exponentially with respect to the bias voltage, so the rate of increase in current is large. Therefore, by increasing the potential of the power supply 15,
The current flowing through the Schottky diode 13 or 14 decreases rapidly. If node 8 is High
level, the short-circuit current flows through two paths: one from the node 8 through the gate and source of the driver FET 4 to GND, and the other through the short-circuit diode 14 to the power supply 15.
However, if the current flowing through the Schottky diode 14 is suppressed to below the current flowing through the gate and source of the driver FET by increasing the potential of the power supply 15, the Schottky diode 1
The drop in the potential of node 8 due to the addition of node 4 can be suppressed to a small level. However, since the capacitance due to the addition of the Schottky diode increases as the bias voltage between the anode and cathode increases, it is necessary to select the optimum value for the potential of the power supply 15 from both the amplitude and capacitance.

In this embodiment, shot diodes 14 and 14 are connected to storage nodes 8 and 9 of memory cells.
13 in the forward direction to add capacitance, the capacity of the storage node can be increased by adding a diode to a greater extent than by connecting it in the reverse direction, and the Schottky diode used to reduce soft errors can be The area occupied can be reduced. Moreover, since the added Schottky diode is connected to the power supply 15 which is higher than the ground potential, the forward current of the diodes 14 and 13, which lowers the potential amplitude of the storage nodes 8 and 9, is reduced. It is possible to suppress the decrease in the potential amplitude of the node to a small level, and to prevent the soft error reduction effect from being inhibited or the noise margin from decreasing due to the decrease in the potential amplitude.

Note that in the above embodiment, the gate/load element is used as a load element.
Although a memory cell using a normally-on MESFET with a common source has been described, this may be a resistive load type memory cell as shown in FIG. 2, and the same effects as in the above embodiment can be obtained.

In addition, in the above embodiment, the memory cell driver
Although the case has been described in which the source of the FET is grounded, this potential may be any potential other than the ground potential, and the same effects as in the above embodiments can be achieved.

〔Effect of the invention〕

As described above, according to the gallium arsenide semiconductor memory device of the present invention, a Schottky diode is forwardly connected to the storage node of a memory cell to add capacitance, and the cathode potential of the Schottky diode is lowered to a lower level than the memory cell. Since the potential is higher than the potential side power supply, the capacity increase of the storage node due to connection of the diode is greater than when connected in the reverse direction, and the area occupied by the Schottky diode used for soft error reduction on the board can be reduced. Moreover, by increasing the cathode potential, the forward current of the diode that lowers the potential amplitude of the storage node is reduced, thereby suppressing the decrease in the potential amplitude of the storage node and increasing the potential amplitude. There is an effect that it is possible to avoid inhibiting the soft error reduction effect and reducing the noise margin due to the decrease.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a memory cell of a gallium arsenide semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is a circuit configuration diagram showing a memory cell of a gallium arsenide semiconductor memory device according to another embodiment of the present invention;
FIG. 3 is a circuit configuration diagram showing a memory cell of a conventional gallium arsenide semiconductor memory device, FIG. 4 is a diagram showing the transfer characteristics of an E/D inverter in a memory cell of a conventional gallium arsenide semiconductor memory device, and FIG. 1 is a configuration diagram showing a circuit in which a Schottky diode is used to add capacitance to a memory cell of a conventional gallium arsenide semiconductor memory device; FIG. In the figure, 1 and 2 are normally-on MESFETs, and 3
to 6 are normally-off MESFETs, 7, 15
is the power supply, 8 and 9 are storage nodes, 10 and 11
12 is a bit line, 12 is a word line, 13 and 14 are shotgun diodes, and 16 and 17 are resistance elements. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. Two inverter circuits formed on a gallium arsenide substrate and consisting of a load element and a MESFET connected in series are connected in parallel between a high potential side power source and a low potential side power source, and each of the above inverter circuits is In a gallium arsenide semiconductor memory device in which inputs and outputs are cross-connected to form a flip-flop type memory cell in which each connection point serves as a storage node, a Schottky diode is connected to each storage node of the memory cell so that this serves as an anode. A gallium arsenide semiconductor memory device, characterized in that the Schottky diodes are connected in a forward direction to add a capacitance to the node, and the cathode of each Schottky diode is connected to a third power source having a higher potential than the low potential side power source.